• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1242-1249
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• 2012

This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.

• The Journal of the Acoustical Society of Korea
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• v.9 no.2
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• pp.61-69
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• 1990

We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confirmed the relization of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.7
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• pp.816-823
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• 2018

The Auto-synchronizer is essential equipment for synchronizing a generator to the power system. It is performing that measurement of the magnitude, frequency and phase of the voltage signal of the power system and generator. It is important to select the appropriate measurement algorithm for preventing various problem such as mechanical stress and Electrical problem. Teager Energy Operator(TEO) and Discrete separation algorithm(DESA) is measurable the instantaneous parameters of a sine wave using 5 samples and can be measured at a fast and with a simple operation. Therefore it has many advantages in measuring the parameters. In this paper, it confirmed measurement results using matlab simulations when there are synchronized in order of frequency, magnitude. Also it presented methods using digital filters and sample intervals to improve accuracy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.481-487
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• 2013

To successfully accomplish a bit synchronization, a synchronizer should exploit a preamble pattern. A MFM (modified frequency modulation) flag is uses as a preamble in a PJM (phase jitter modulation) mode RFID standard. In the recent work, a synchronizer for a PJM mode tag was proposed, which is composed of several correlators. In this paper, we present a new bit synchronizer in which a coarse synchronization is done as in the previous work while a fine synchronization is performed via exploiting a violation bit included in the MFM flag. We show that the proposed synchronizer can significantly reduce the overall hardware complexity at the expense of slight burden to a demodulator structure. Through simulation, we also show that its performance is comparable to that of the previous system despite its hardware simplicity.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.2
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• pp.77-83
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• 2011

In this paper, we present the design procedure of the synchronizer and the demodulator of a 13.56MHz RFID PJM tag, which was standardized in ISO 18000-3 mode 3. We optimize the algorithms in order to minimize the number of registers and implement them based on international standard. The designed module is simulated by Modelsim and FPGA. The synchronizer is composed of 3 correlators that is implemented by 1,024(16bit ${\times}$ 64cycle) registers. The demodulator is composed of 2 correlators that is implemented by 128(2bit ${\times}$ 64cycle) registers. The simulation performed with the demodulator integrated with the synchronizer shows that it works at about 87% success rate with the test data of SNR -2dB and 100% with those of SNR 4dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.12
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• pp.1044-1052
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• 1990

We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confrmed the realiation of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

• Journal of Communications and Networks
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• v.14 no.5
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• pp.501-509
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• 2012

This paper proposes a joint timing synchronization, channel estimation, and data detection for the impulse radio ultra-wideband systems. The proposed timing synchronizer consists of coarse and fine timing estimation. The synchronizer discovers synchronization points in two stages and performs adaptive threshold based on the maximum pulse averaging and maximum (MAX-PA) method for more precise synchronization. Then, iterative channel estimation is performed based on the discovered synchronization points, and data are detected using the selective rake (S-RAKE) detector employing maximal ratio combining. The proposed synchronizer produces two signals-the start signal for channel estimation and the start signal for start frame delimiter (SFD) detection that detects the packet synchronization signal. With the proposed synchronization, channel estimation, and SFD detection, an S-RAKE receiver with binary pulse position modulation binary phase-shift keying modulation was constructed. In addition, an IEEE 802.15.4a channel model was used for performance comparison. The comparison results show that the constructed receiver yields high performance close to perfect synchronization.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.10
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• pp.1123-1130
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• 2015

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

• Journal of the Society of Naval Architects of Korea
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• v.53 no.5
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• pp.371-379
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• 2016

In the ship design process, ship motion and propulsion performance in sea waves became very important issues. Especially, prediction of ship propulsion performance during real operation is an important challenge to ship owners for economic operation in terms of fuel consumption and route-time evaluation. Therefore, it should be considered in the early design stages of the ship. It is thought that the averaged value and fluctuation of effective inflow velocity to the propeller have a great effect on the propulsion performance in waves. However, even for the nominal velocity distribution, very few results have been presented due to some technical difficulties in experiments. In this study, flow measurements near the propeller plane using a stereo PIV system were performed. Phase-averaged flow fields on the propeller plane of a KVLCC2 model ship in waves were measured in the towing tank by using the stereo PIV system and a phase synchronizer with heave motion. The experiment was carried out at fully loaded condition with making surge, heave and pitch motions free at a forward speed corresponding to Fr=0.142 (Re=2.55×106) in various head waves and calm water condition. The phase averaged nominal velocity fields obtained from the measurements are discussed with respect to effects of wave orbital velocity and ship motion. The low velocity region is affected by pressure gradient and ship motion.