• Progress in Medical Physics
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• v.3 no.2
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• pp.43-57
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• 1992

Phase detector techique provides a unique probe to membrane recycling phenomenon by enabling dynamic monitoring of cell membrane capacitance. However, it has inherent errors due to constant changes in measurement environments. The present study analyzed several error sources to develope application criteria of this technique. and the following was found based on a theoretical analysis. The initial phase angle has to be appropriately selected to minimize the error due to perturbation of access and membrane conductances. Excitation frequency is also important to determine the initial phase angle. However. deviation of the phase angle from a predetermined initial value during the measurement period does not affect capacitance estimation to a significant degree. Despite an appropriate initial phase selection an error in scaling factor is expected for a large increase in capacitance during exocytosis. which may be overcome by iteratively correcting the scaling factor over the measurement period. These results will provide a useful guideline in practical application of this technique.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.8-14
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• 1992

In this paper, the differential detection technique of multi-h CPM is introduced and described. We derived the sets of modulation index of multi-h phase codes adequate to the differential detection. The power spectra of multi-h signals with various sets of modulation index are presented and compared to those of MSK and QPSK. Error rate performances of the conventional detector and Viterbi algorithm detector of 2-h and 3-h CPM are evaluated and compared.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.1-8
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• 2000

This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.46-52
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• 2014

This paper presents a multiple gain controlled digital phase and frequency detector with a fast lock-time. Lock-time of the digital PLL can be significantly reduced by applying proposed adaptive gain control technique. A loop gain of the proposed digital PLL is controlled by three conditions that are very large phase difference between reference and feedback signal, small phase difference and before lock-state, and after lock-state. The simulation result shows that lock-time of the proposed multiple gain controlled digital PLL is 100 times faster than that of the conventional structure with unit gain mode.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.24-33
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• 2002

For mixed signal circuits that integrate both analog and digital blocks onto the same chip, testing the mixed circuits has become the bottleneck. Since most of mixed signal circuits are functionally tested, mixed signal testing needs expensive automatic test equipments for test input generation and response acquisition. In this paper, a new efficient BIST is developed which can be used for mixed signal circuits. In the new BIST, only faults on embedded resistances, capacitances and its combinations are considered. To guarantee the quality of chips, the new BIST performs both voltage testing and phase testing. Using these two testing modes, all the faults are detected. In order to support this technique, the voltage detector and the phase detector are developed. Experimental results prove the efficiency of the new BIST.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.6
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• pp.128-135
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• 1996

This paper proposes a high precision measurement technique to obtain the height of gage block with a few millimeter height. The proposed technique is consisted of two steps : In the first step, laser position transducer and electric micrometer are adopted to obtain a coarse value of the height of gage block, and then, in the second step, heterodyne laser interferometry is adopted to acquire the precision value. A new kind of phase detector is constructed in the low cost for the heterodyne interferometer and its linearity with ${\pm}1%$ is confirmed by experiment. Also measurement error factors due to enviroments are discussed and methodology to reduce such errors is proposed. Preliminary experiments are carried out for the gage blocks of as high as a few millimeter.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.2006-2009
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• 2005

This paper presents a method for registering images using phase correlation technique in fourier domain, hough transform and multi-resolution wavelet. To register images, source and input images are transformed to wavelet domain. An angular transition can be obtained by applying hough transform technique followed by phase correlation. Then we apply phase correlation technique to find x-axis and y-axis transition. We apply wavelet transform to reduce processing time and also use its coefficients as edge information instead of canny detector. With multi-resolution property of wavelet transform, registration time can be greatly reduced. After we get all transition parameters, we transform the input images according to these parameters. Then, we compose and blend all images into a new large image with details of all source images. From our experiment, we can find the accurate transition both x-y translation and angular transition with less error.

• Journal of Navigation and Port Research
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• v.36 no.5
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• pp.371-378
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• 2012

This paper presents a timing recovery method using Gardner TED (Timing Error Detector) with a Peak Detector using Parabola Peak Interpolation in underwater acoustic communication. This method will have an eye to improve phase converge speed of timing recovery and reduced amount of Tx data. The OQPSK(Offset Quadrature Phase Shift Keying) modulation technique was considered. The proposed algorithm has faster recovery speed and more accurate than Gardner TED because the sampling values in the proposed algorithm are moved persistingly to maximum or minimum point using parabolic peak interpolation. when simulation performed using Preposed method, it improved BER (Bit Error Rate) performance about 23% And to evaluate the performances of the proposed algorithm the sea trial was performed in the Korean East Sea. And distance of a transmitter-receiver is 3 km each other. As a result, the proposed algorithm outperforms better BER performance about 20% of timing recovery than the Gardner method. Also Proposed method improved converge speed of timing recovery about 1.4 times better than Gardner method.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.