• Title/Summary/Keyword: Phase Errors

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Analysis of the monopulse radar tracking errors according to the JSR of cross-eye jammer and radar reflection signals (크로스아이 재머와 레이다 반사 신호 비(JSR)에 따른 모노펄스 레이다 추적 오차 분석)

  • Lim, Joong-Soo;Chae, Gyoo-Soo
    • Journal of Convergence for Information Technology
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    • v.11 no.8
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    • pp.23-28
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    • 2021
  • In this paper, we analyze the tracking errors of monopulse radar according to the JSR of retrodirective cross-eye and radar skin return signals. The cross-eye jammer gain(Gc) is used to calculate the radar tracking errors, and the relationship between the jammer gain and the JSR is represented mathematically. We analyze the radar tracking errors by varying the tracking angle and JSR. Analysis results of the phase difference(ϕ) and amplitude ratio(a) between the two jammer signals and the changing JSR show that the closer the phase difference of the two jammer signals is to 180, the greater the tracking error and it shows that if the JSR is above 20dB, the tracking errors no longer increase. This work presents an effective utilization of retrodirective cross-eye jammers through various tracking error analyses based on the JSR, tracking angles, two-jammer phase differences and amplitude ratios of two-jammer signals.

Errors of Proportional Shifting due to Simplified Equivalent Circuit of a 3-Phase Induction Motor (3상유도전동기의 간이등가회로에 의한 비례추이 오차)

  • Shin, Myoung-Ho
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.1
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    • pp.109-112
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    • 2013
  • It is well known that the maximum torque of a 3-phase induction motor does not vary as the resistance of rotor varies by proportional shifting. However, proportional shifting is derived using simplified equivalent circuit of induction motor. Therefore, there are some errors in the torque characteristics shown in the text book. This paper presents the torque characteristics using not simplified equivalent circuit but equivalent circuit. Errors produced by simplified equivalent circuit are presented.

System Performance with Synchronization Errors in Distributed Beamforming Systems (분산 빔포밍을 이용한 시스템에서 동기에러에 의한 시스템 성능 영향 분석)

  • Kim, Haesoo;Kwon, Seong-Geun
    • Journal of Korea Multimedia Society
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    • v.18 no.4
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    • pp.452-459
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    • 2015
  • Three synchronization issues, i.e., phase, frequency, and symbol time, have to be properly controlled to achieve distributed beamforming gain. In this paper, the impacts of synchronization errors in distributed beamforming are analyzed for both single-carrier and OFDM systems. When the channel is constant over a symbol duration, the performance degradation due to phase offset is the same for both single-carrier and OFDM systems. For symbol timing offset in OFDM systems, high frequency subcarriers are more susceptible as compared to low frequency ones. Frequency offset is critical in OFDM systems since it leads to interference from the other subcarriers as well as power loss in the desired signal.

Correction Simulation for Metal Patterns on Attenuated Phase-shifting Lithography

  • Lee, Hoong-Joo;Lee, Jun-Ha
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.3
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    • pp.104-108
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    • 2004
  • Problems of overlap errors and side-lobe printing by the design rule reduction in the lithography process using attenuated phase-shifting masks(attPSM) have been serious. Overlap errors and side-lobes can be simultaneously solved by the rule-based correction using scattering bars with the rules extracted from test patterns. Process parameters affecting the attPSM lithography simulation have been determined by the fitting method to the process data. Overlap errors have been solved applying the correction rules to the metal patterns overlapped with contact/via. Moreover, the optimal insertion rule of the scattering bars has made it possible to suppress the side-lobes and to get additional pattern fidelity at the same time.

Performance Improvement Analysis of DS-CDMA Systems Employing a Partial Multistage Interference Canceller with Timing and Phase Errors (칩 동기 에러와 위상 에러가 존재하는 환경에서 부분 다단 간섭제거기를 채용하는 DS-CDMA 시스템의 성능 개선 분석)

  • 김봉철;강근정;오창헌;조성준
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2000.11a
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    • pp.7-11
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    • 2000
  • 본 논문에서는 불완전 동기(Imperfect Synchronization)로 인한 칩 동기 에러(timing errors)와 위상 에러(phase errors)를 고려 하여 비동기(Asynchronous) DS-CDMA 시스템의 성능을 이론적으로 분석하였다. 성능 개선 기법으로는 다단 간섭제거기 (Multistage PIC)와 부분 다단 간섭제거기(Partial Multistage PIC)를 채용하였고 칩 동기 에러와 위상 에러가 두 간섭제거기의 간섭제거능력에 미치는 영향의 정도를 정량적으로 분석하였다. 성능분석 결과로부터 칩 동기 에러와 위상 에러로 인한 1단(no cancellation)에서의 성능 열화가 각 단의 상관기 출력(decision statistic)에 영향을 줌으로써 다단 간섭제거기와 부분 다단 간섭제거기의 성능 개선폭을 감소시켰다. 그렇지만, 불완전 동기에도 불구하고 단(stage) 수가 증가할수록 두 간섭제거기 모두 강한 간섭제거능력을 보였다. 실제 시스템에서는 성능 개선과 구현상의 복잡도를 동시에 고려해야하므로 다단 간섭제거기 보다 구조가 간단하고 계산량이 적은 부분 다단 간섭제거기의 활용도가 높아질 것이 예상된다.

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Development of Standard Activity Model for Small and Medium sized Plant: Focused on Detailed Design Phase (중소형 플랜트의 표준화된 플랜트 엔지니어링 활동 모델 개발: 상세설계를 중심으로)

  • Shin, Jung Uk;Yeom, Choong Sub
    • Journal of the Korean Society of Systems Engineering
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    • v.14 no.1
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    • pp.13-18
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    • 2018
  • Plant Engineering is a series of activities going through following life cycle phases: planning, basic design, detailed design, procurement and construction, commissioning, operation and maintenance, to produce a target product. From among these phases of plant engineering life cycle, a detailed design phase is an important phase producing final design deliveries. Luckily, through technical co-operation and experiences of constructing plants, large Korean engineering companies have accumulated know-hows of efficient detailed designs. However, smaller engineering companies have less experience of performing detailed designs so there is always a risk of causing design errors in the detailed design phase. To mitigate the risk of design errors in the detailed design phase, it is necessary to systematize a concrete activity model of a detailed design phase. In this paper, we have developed a prototype of a detailed design activity model through a widely used function modeling methodology called IDEF0.

Accurate Characterization of T/R Modules with Consideration of Amplitude/Phase Cross Effect in AESA Antenna Unit

  • Ahn, Chang-Soo;Chon, Sang-Mi;Kim, Seon-Joo;Kim, Young-Sik;Lee, Juseop
    • ETRI Journal
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    • v.38 no.3
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    • pp.417-424
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    • 2016
  • In this paper, an accurate characterization of a fabricated X-band transmit/receive module is described with the process of generating control data to correct amplitude and phase deviations in an active electronically scanned array antenna unit. In the characterization, quantization errors (from both a digitally controlled attenuator and a phase shifter) are considered using not theoretical values (due to discrete sets of amplitude and phase states) but measured values (of which implementation errors are a part). By using the presented procedure for the characterization, each initial control bit of both the attenuator and the phase shifter is closest to the required value for each array element position. In addition, each compensated control bit for the parasitic cross effect between amplitude and phase control is decided using the same procedure. Reduction of the peak sidelobe level of an array antenna is presented as an example to validate the proposed procedure.

Gate CD Control for memory Chip using Total Process Proximity Based Correction Method

  • Nam, Byung--Ho;Lee, Hyung-J.
    • Journal of the Optical Society of Korea
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    • v.6 no.4
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    • pp.180-184
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    • 2002
  • In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch conditions. We propose that total process proximity correction (TPPC), a concept merging every process step error correction, is essential in a lithography process when minimum critical dimension (CD) is smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.

Compensation of Cross Talk Error for Optical Voltage Sensors

  • Cho, Jae-Kyong
    • Journal of the Optical Society of Korea
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    • v.11 no.4
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    • pp.177-182
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    • 2007
  • This paper discusses the errors associated with electric field cross talk for optical voltage sensors in a three-phase electric system and provides a solution to compensate the errors. For many practical conductor configurations, the electric field cross talk may cause errors unacceptable for the accuracy requirements of the sensors. We devised a real time compensation method for the cross talk and built an electronic circuits based on it. The mechanism of the compensation and the corresponding error reduction were discussed.

Optical Current Measuring System for Compensating Interference by Adjacent Electric Wires

  • Cho, Jae-Kyong
    • Journal of Magnetics
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    • v.12 no.4
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    • pp.156-160
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    • 2007
  • In this paper, we analyze the errors associated with magnetic field interference for fiber-optic current sensors working in a three-phase electric system and provide a solution to compensate the interference. For many practical conductor arrangements, the magnetic filed interference may cause errors unacceptable for the accuracy requirements of the sensors. We devised a real time compensation method for the interference by introducing geometric and weight factors. We realized the method using simple electronic circuits and obtained the real time compensated outputs with errors of ${\pm}1%$.