• Journal of KIISE:Information Networking
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• v.29 no.5
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• pp.562-572
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• 2002

Distributed object technologies have become popular in developing distributed systems. Although such middleware platforms as DSOM, DCOM, CORBA and Java RMI ease the development of distributed applications, they do not directly improve the reliability and the availability of these applications. Because the task of developing fault-tolerance techniques for distributed object paradigms is often complicated and error-prone, there is a great need for a development toolkit that enhances the reliability and the availability of distributed objects. In this paper, we propose a fault-tolerant distributed middleware system based on RMI, called IMMORTAL. We use a log-based rollback-recovery mechanism for supporting reliable distributed computing. Through a series of experiments, we observe that benchmark applications on the IMMORTAL tolerate hardware and software failures and evaluate its performance and scalability.

• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1371-1379
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• 1997

Undetectable faults in a digital circuit are faults that no input patterms can detect.Identifying these faults in test geferation process is very time- consuming especially for sequential circuits .In this paper we present a new algorithm to identify unedtectable faults in sequential cirouits .In the alorithm. we identify uninitializable fip-flops and then, faults that prevent intialization of the fkip-flops(FPIs)are identified, finally propagation path of the FPI is checked. Time complexity of this algorithm is porportional to the product of the number of flip flops with at lest a self loop and the number of gates in the circuit. Experiments were performed on the ISCAS89 benchmark ciruits to show the feadibility of the proposed algorithm.We could identify large amount of undetectable faults(up to 50% of the number of flip-flops)in circuits with uninitializable flip-flops. Consider-ing that most of the time in test generation is cinsumed in identifying undetecatable faults, performance of test generator can be improved by using this algorithm as a pre-processing of test generation.

• The KIPS Transactions:PartB
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• v.16B no.5
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• pp.359-366
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• 2009

Analysis of 3-dimensional (3D) protein structure plays an important role of structural bioinformatics. The protein structure alignment is the main subjects of the structural bioinformatics and the most fundamental problem. Protein Structures are flexible and undergo structural changes as part of their function, and most existing protein structure comparison methods treat them as rigid bodies, which may lead to incorrect alignment. We present a new method that carries out the flexible structure alignment by means of finding SSPs(Similar Substructure Pairs) and flexible points of the protein. In order to find SSPs, we encode the coordinates of atoms in the backbone of protein into RDA(Relative Direction Angle) using local similarity of protein structure. We connect the SSPs with Floyd-Warshall algorithm and make compatible SSPs. We compare the two compatible SSPs and find optimal flexible point in the protein. On our well defined performance experiment, 68 benchmark data set is used and our method is better than three widely used methods (DALI, CE, FATCAT) in terms of alignment accuracy.

• KIPS Transactions on Software and Data Engineering
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• v.4 no.4
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• pp.187-194
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• 2015

In this paper, we present an effective visual odometry estimation system to track the real-time pose of a camera moving in 3D space. In order to meet the real-time requirement as well as to make full use of rich information from color and depth images, our system adopts a feature-based sparse odometry estimation method. After matching features extracted from across image frames, it repeats both the additional inlier set refinement and the motion refinement to get more accurate estimate of camera odometry. Moreover, even when the remaining inlier set is not sufficient, our system computes the final odometry estimate in proportion to the size of the inlier set, which improves the tracking success rate greatly. Through experiments with TUM benchmark datasets and implementation of the 3D scene reconstruction application, we confirmed the high performance of the proposed visual odometry estimation method.

• Progress in Superconductivity
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• v.12 no.2
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• pp.75-81
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• 2011

We report on the progress that has been made in developing $MgB_2$ superconducting wires and tapes for commercialization and research efforts. A number of techniques have been developed to overcome the obstacle posed by the poor critical current density ($J_c$) of pristine $MgB_2$. Chemical doping has proved to be the effective way to modify and enhance the superconducting properties, such as the $J_c$ and the irreversibility field ($B_{irr}$). More than 100 different types of dopants have been investigated over the past 8 years. Among these, the most effective dopants have been identified to be SiC and malic acid ($C_4H_6O_5$). The best results, viz. a $B_{irr}$ of 22 T and $J_c$ of $30,000\;A{\cdot}cm^{-2}$ at 4.2 K and 10 T, were reported for malic acid doped $MgB_2$ wires, which matched the benchmark performance of commercial low temperature superconductor wires. In this work, we discuss the progress made in $MgB_2$ conductors over the past few years at the University of Wollongong, Hyper Tech Research, Inc., and Ohio State University.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.71-78
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• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

• Journal of the Korea Society of Computer and Information
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• v.25 no.7
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• pp.47-55
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• 2020

In this paper, we propose one stage multi-scale face detector based Fully Convolution Network using anchor free method. Recently almost all state-of-the-art face detectors which predict location of faces using anchor-based methods rely on pre-defined anchor boxes. However this face detectors need to hyper-parameters and additional computation in training. The key idea of the proposed method is to eliminate hyper-parameters and additional computation using anchor free method. To do this, we apply two ideas. First, by eliminating the pre-defined set of anchor boxes, we avoid the additional computation and hyper-parameters related to anchor boxes. Second, our detector predicts location of faces using multi-feature maps to reduce foreground/background imbalance issue. Through Quantitative evaluation, the performance of the proposed method is evaluated and analyzed. Experimental results on the FDDB dataset demonstrate the effective of our proposed method.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.2
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• pp.137-147
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• 2003

The fuzzy control and implementation of a new three-dimensional(3-D) inverted pendulum system are addressed. In comparison with conventional 1-D and 2-D systems, the 3-D inverted pendulum system is a proper benchmark system to simulate human's control action which includes the up and down motion to stabilize an inverted pendulum. To investigate the characteristics of the 3-D inverted pendulum system and to design of a fuzzy controller, we derive dynamic equations of the mechanism including a 3-axis cartesian robot and an inverted pendulum. We propose a design method of a fuzzy controller of the yaw and pitch angles of an inverted pendulum. In the design, the redundant degree-of-freedom(DOF) of the robot and the constrained workspace are taken into account. The performance of the proposed system is proved by experimental results using a developed PC-based Multi-Motion Control(MMC) board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.28-36
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• 2009

Sequence-Pair(SP) model represents the topological relation between modules. In general, SP model based floorplanners search solutions using Simulated-Annealing(SA) algorithm. Several SA based floorplanning techniques using SP model have been published. To improve the performance of those techniques they tried to improve the speed for evaluation function for SP model, to find better scheduling methods and perturb functions for SA. In this paper we propose a two phase SA based algorithm. In the first phase, white space between modules is reduced by applying compaction technique to the floorplan obtained by an SP. From the compacted floorplan, the corresponding SP is determined. Solution space has been searched by changing the SP in the SA framework. When solutions converge to some threshold value, the first phase of the SA based search stops. Then using the typical SA based algorithm, ie, without using the compaction technique, the second phase of our algorithm continues to find optimal solutions. Experimental results with MCNC benchmark circuits show that how the proposed technique affects to the procedure for SA based floorplainning algorithm and that the results obtained by our technique is better than those obtained by existing SA-based algorithms.