• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.5
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• pp.289-293
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• 2016

The flux-lock type superconducting fault current limiter (SFCL) connects the two parallel windings in parallel with a ferromagnetic core. We suggest that the double quench flux-lock type SFCL should add a third winding. We analyzed characteristics of the fault current and the peak current using the quench of the high-Tc superconducting element. The proposed SFCL's inductances of a primary winding and the third winding were fixed and the amplitude of inductance of the secondary winding was changed. We found that the fault current can be more effectively controlled through the analysis of the equivalent circuit and the short-circuit tests.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.171-174
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• 1991

Among the various PWM methods, the hysteresis-band current control PWM method is popularly used because of its simplicity of implementation, fast response characteristics and inherent peak current limiting capability. However, the current control PWM method with a fixed hysteresis-band has the disadvantage that switching frequency decreases and current ripple is high as the increasing of back-EMF. As a result, load current contains excess harmonics. This paper describes a adaptive hysteresis-bandwidth control algorithm so as to maintain the average switching frequency constant and decrease the current ripple where the hysteresis bandwidth is derived as a relation with the switching frequency. This control algorithm is applied to the surface-type brushless DC motor with separated winding and using the computer simulation, the validity of its algorithm is proved.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1298-1305
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• 2016

This paper presents the development of a short-circuit protection mechanism on a high voltage switch (HVS) board which is built by a series connection of semiconductor switches. The HVS board is able to quickly detect and limit the peak fault current before the signal board triggers off a gate signal. Voltage clamping techniques are used to safely turn off the short-circuit current and to prevent overvoltage of the series-connected switches. The selection method of the main devices and the development of the HVS board are described in detail. Experimental results have demonstrated that the HVS board is capable of withstanding a short-circuit current at a rated voltage of 10kV without a di/dt slowing down inductor. The corresponding short-circuit current is restricted to 125 A within 100 ns and can safely turn off within 120 ns.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.90-94
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employes active and reactive power control or frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employes a instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Futhermore, the proposed control scheme is verified through the simulation in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.176-181
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• 1998

The parallel inverter is popularly used because of its fault-tolerance capability, high-current outputs at constant voltages and system modularity. The conventional parallel inverter usually employs active and reactive power control of frequency and voltage droop control. However, these approaches have the disadvantages that the response time of parallel inverter control is slow against load and system parameter variation to calculate active, reactive power, frequency and voltage. This paper describes a novel control scheme for power equalization in parallel-connected inverter. The proposed scheme has a fast power balance control response, a simplicity of implementation, and inherent peak current limiting capability since it employees an instantaneous current/voltage control with output voltage and current balance and output voltage regulation. A design procedure for the proposed parallel inverter controller is presented. Furthermore, the proposed control scheme is verified through the experiment in various cases such as the system parameter variation, the control parameter variation and the nonlinear load condition.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.802-807
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• 1998

The main drawback of parallel type active power filters (APF) is the large capacity required for harmonic compensation. This paper evaluates the APF capacity requirement of harmonic/reactive power compensation for thyristor converter load. Theoretically achievable maximum power factor under partial load is evaluated. And it is shown that the APF capacity can be considerably reduced while slightly sacrificing the filtering performance by deliberately limiting the peak current of the APF.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.12
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• pp.715-726
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• 1999

This paper estimates the capacity of shunt type active power filters(APF) for harmonic/reactive power compensation with a thyristor converter load. The base capacity requirement of APF is defined for idealized converter load current waveform and the effect of commutation overlap on the APF capacity is examined. The APF capacity required for reactive power compensation in addition to the harmonic elimination is estimated to give maximum achievable power factor for various operating condition of the partially-loaded thyristor converter. The method of current limit of APF is introduced, and it is shown that the APF capacity can be considerably reduced by deliberately limiting the peak current while maintaining the filtering performance to meet the level std 519 regulation.

• Progress in Superconductivity and Cryogenics
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• v.23 no.3
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• pp.51-54
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• 2021

The DC system has less power loss compared to the AC system because there is no influence of frequency and dielectric loss. However, the zero-crossing point of the current is not detected in the event of a short circuit fault, and it is difficult to interruption due to the large fault current that occurs during the opening, so the reliability of the DC breaker is required. As a solution to this, an LC resonance DC circuit breaker combined a superconducting element has been proposed. This is a method of limiting the fault current, which rises rapidly in case of a short circuit fault, with the quench resistance of the superconducting element, and interruption the fault current passing through the zero-crossing point through LC resonance. The superconducting current limiting element combined to the DC circuit breaker plays an important role in reducing the electrical burden of the circuit breaker. However, at the beginning of a short circuit fault, superconducting devices also have a large electrical burden due to large fault currents, which can destroy the element. In this paper, the reactor is connected to the source side of the circuit using PSCAD/EMTDC. After that, the change of the fault current according to the reactor capacity and the electrical burden of the superconducting element were confirmed through simulation. As a result, it was confirmed that the interruption time was delayed as the capacity of the reactor connected to the source side increased, but peak of the fault current decreased, the zero-crossing point generation time was shortened, and the electrical burden of the superconducting element decreased.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.348-351
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• 1999

We investigated current limiting properties for an SFCL of YBCO thin film coated with an Au layer. The YBCO film of 1 mm wide and 400 nm thick could carry the current 9.6 A$_{peak}$ without quench. The SFCL limited the fault current below 7.6 A$_{peak}$, which otherwise increases above 65 A$_{peak}$ and melted down at the potential fault current of about 100 A$_{peak}$ which is 10 times greater than the quench current. This means that the Au layer successfully protected the superconducting film by dispersing the heat generated at hot spots and electrically shunting the YBCO film.

• Progress in Superconductivity
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• v.5 no.2
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• pp.136-140
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• 2004

We fabricated and tested a resistive superconducting fault current limiters (SFCL) operated at 3.8 ㎸ based on YBCO thin films. The SFCL was composed of 7 components connected in series. Each component was designed to be capable of current limiting at 600 V, and has a SiC shunt resistor ( $R_{s}$) of 40 Ω in Parallel. Short circuit tests were carried out fur 0 and 90 degree faults lasting fur 5 cycles. The test results showed that the 7 components were quenched simultaneously under the safe quenches and evenly shared the applied voltage. The SFCL successfully suppressed the fault currents below 94 $A_{peak}$ within the quarter cycle after fault.t.t.