• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.821-825
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• 2004

The a-Si：H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si：H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN：H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN：H (2000 ), a-Si：H(2000 ) and n+a-Si：H (500). We have deposited n+a-Si：H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si：H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si：H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.74-74
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• 2009

The ArF PR mask was. developed to overcome the limit. of sub 40nm patterning technology with KrF PR. But ArF PR difficult to meet the required PR selectivity by thin PR thickness. So need to the multi-stack mask such as amorphous carbon layer (ACL). Generally capacitively coupled plasma (CCP) etcher difficult to make the high density plasma and inductively coupled plasma (ICP) type etcher is more suitable for multi stack mask etching. Hybrid Coupled Plasma source (HCPs) etcher using the 13.56MHz RF power for ICP source and 2MHz and 27.12MHz for bias power was adopted to improve the process capability and controllability of ion density and energy independently. In the study, the oxide trench which has the multi stack layer process was investigated with the HCPs etcher (iGeminus-600 model DMS Corporation). The results were analyzed by scanning electron microscope (SEM) and it was found that etching characteristic of oxide trench profile depend on the multi-stack mask.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.687-687
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• 2013

In rearpoint contact solar cell and the PERC (passivated emitter rear contact) type cell, surfaces were passivated by SiO2 or Al2O3 to increase solar cell efficiency. Therefore, we have investigated the effect of surface passivation for crystalline silicon solarcell using mass-production atomic layer deposited (ALD) Al2O3. The patttern which consists of cylinders with 100um diameter and 5um height was formed by PR patterning on Si (100) substrate and then Al2O3 of about 10nm and 20nm thickness was deposited by ALD. The pattern in 10 nm Al2O3 film was removed by dipping in aceton solution for about 10 min but the pattern in 20 nm Al2O3 film was not. The influences of process temperature and heat treatment were investigated using microwave photoconductance decay (PCD) and Quasi-Steady-State photoconductance (QSSPC). The solar cell process used in this work combines the advantage of using the applicability of a selective deposition associated with a ALD passivation and the use of low-cost screen print for the contacts formation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.190-193
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• 2002

The processing technology of organic thin-film transistors (Ons) performances have improved fur the last decade. Gate insulator layer has generally used inorganic layer, such as silicon oxide which has properties of a low electrical conductivity and a high breakdown field. However, inorganic insulating layers, which are formed at high temperature, may affect other layers termed on a substrate through preceding processes. On the other hand, organic insulating layers, which are formed at low temperature, dose not affect pre-process. Known wet-processing methods for fabricating organic insulating layers include a spin coating, dipping and Langmuir-Blodgett film processes. In this paper, we propose the new dry-processing method of organic gate dielectric film in field-effect transistors. Vapor deposition polymerization (VDP) that is mainly used to the conducting polymers is introduced to form the gate dielectric. This method is appropriate to mass production in various end-user applications, for example, flat panel displays, because it has the advantages of shadow mask patterning and in-situ dry process with flexible low-cost large area displays. Also we fabricated four by four active pixels with all-organic thin-film transistors and phosphorescent organic light emitting devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.97-104
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• 1996

Because of the novel characteristics such as chemical stability, hardness, electrical resistivity and thermal conductance, diamond-like carbon (DLC) film is a suitable materials for the passivation layers. For this purpose, DLC films are synthesized under various conditions and are characterized. Adhesive stregth is excellent and increased with the increase of the hydrogen gas flow rate. The resistivity of approximately 5.3X10$^{8}{\Omega}{\cdot}cm$ is measured by automatic spreading resistance probe analysis method. The thermal conductivity of DLC films is superior to that of PSG oxide and improved by increasing the hydrogen gas flow rate. The patterning techniques of the DLC films is developed using the lift-off and RIE methods to form 5${\mu}$m line. Finally, power transistor with the DLC film as passivation layer is fabricated and analyzed. The test result shows the improsved long-term stability and higher breakdown voltage.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.1
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• pp.27-31
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• 2009

In this paper, the polymer adhesive bonding technology using wafer-level technology was investigated and warpage results were analyzed. Si and glass wafer was bonded after adhesive polymer layer and dam pattern for uniform state was patterned on glass wafer. In this study, warpage result decreased as the low of bonding temperature of Si wafer, bonding pressure and height of adhesive bonding layer. The availability of adhesive polymer bonding was confirmed by TC, HTC, Humidity soak test after dicing. The result is that defect has not found without reference to warpage.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.12
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• pp.177-184
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• 2001

C3M(chemical mechanical micro machining) is applied for diminishing the size of burr and fabricating the massless patterning for aluminium wafer(thickness of 1${\mu}m$). It is difficult to perform the micro size machining with the radically increased shear stress. While the miniaturization and function-orientation of parts has been needed in the many field such as electronics, optics and medicine. etc., it is not enough to satisfy the industry needs in the machining technology. In this paper feasibility test of diminishing burr and fabricating maskless pattern was experimented and analyzed. In the experiment oxide layer was farmed on the aluminium with chemical reaction by ${HNO_3}$(10wt%), then the surface was grooved with tungsten carbide tool for the different condition such as the load and fred rate. The result was compared with the conventional machining to show the improvement of C3M with SEM for burr diminish and XPS for atomic existence, AFM for more precise image.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Progress in Superconductivity
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• v.7 no.1
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• pp.6-10
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• 2005

We have studied feasibility of single-layer second-order $high-T_c$ SQUID gradiometers in magnetocardiography. We have measured human cardiomagnetic signals using a short-baseline (5.8 mm) single-layer second-order YBCO gradiometer in partially shielded environments. The gradiometer has an overall size of $17.6\;mm{\times}6\;mm$ and contains three parallel-connected pickup coils which are directly coupled to a step-edge junction SQUID. The gradiometer showed an unshielded gradient noise of $0.84\;pT/cm^2/Hz^{1/2}$ at 1 Hz, which corresponds to an equivalent field noise of $280\;fT/Hz^{1/2}$. The balancing factor was $10^3$. Based on the same design rules as the short-baseline devices, we have studied fabrication of 30 mm-long baseline gradiometers. The devices had an overall size of $70.2\;mm{\times}10.6\;mm$ with each pickup coil of $10\;mm{\times}10\;mm$ in outer size. As Josephson elements we made two types of submicron bridges, which are variable thickness bridge (VTB) and constant thickness bridge (CTB), from $3\;{\mu}m-wide$ and 300 nm-thick YBCO lines with a thin layer of Au on top by using a focused ion beam (FIB) patterning method. VTB was 300 nm wide, 200 nm thick, 30 nm long with Au removed and CTB 100 nm wide and 30 nm long. In temperature-dependent critical currents, $I_c(T)$, VTB showed an nonmetallic barrier-type behavior and CTB an SNS behavior. We believe that those characteristics are ascribed to naturally formed grain boundaries crossing the bridges.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.11
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• pp.1135-1140
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• 2012

Two-step metallization processes have been proposed to achieve high-efficiency silicon solar cells, where the front-side grids are formed by silver plating after the formation of a nickel seed layer with a mask. Because the conventional mask patterning process is performed by an expensive selective printing method using either UV resist or phase change ink, however, the combination of a simple coating and laser-selective ablation processes is proposed in this study as an alternative means. As a masking material, the solar cell wafer was coated with either inexpensive wax having a low melting temperature or a fluorocarbon solution, and then, an electrode image was patterned by selectively removing the masking material using the laser. It was found that the fluorocarbon coating was not only superior to the wax coating in terms of pattern uniformity but it also increased the efficiency of the solar cell by 0.16%, as confirmed by statistical f and t tests.