• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.262-267
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• 2003

At process of production according to development of accumulation degree of semi-conductor element, because functional mistake examination time required increases, is becoming big obstacle factor in cost-cutting. Studied pattern generator that generate pattern and address that is bundle enemy to process these controversial point effectively.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.339-342
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• 2003

An PIAGP generator for TFT-LCD production has been proposed in this paper. The proposed generator was implemented using careful control of timing controller signals using a FPGA. The generator displays successfully the intended pattern sequence(REDlongrightarrowGREENlongrightarrowBLUElongrightarrowWHITElongrightarrowBLACK) and the result are demonstrated at the conference site. The advantage of the use of the proposed generator is the simplification of production equipments and the pattern generator.

• The Transactions of the Korea Information Processing Society
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• v.1 no.2
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• pp.272-278
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• 1994

The paper proposes a test pattern generator and a signature analyzer for pseudoexhaustive testing of the combinational circuit part within a sequential circuit when performing built-in self test of the circuit. The test pattern generator can scan in the seed test pattern and generate exhaustive test patterns. The signature analyzer can perform the analysis of the circuit response and scan out the result. Such test pattern generator and signature analyzer have been developed using SRL(shift register latch) and LFSR(linear feedback shift register).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1537-1545
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• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.45-54
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• 2004

Usually, according as accumulation degree of semi-conductor element increases, dynamic mistake test time increases sharply, and use of pattern generator is essential at manufacturing process to solve these problem. In this paper, we designed the PLD(Programmable Logic Device) circuit of pattern generator to examine dynamic mistake of semi-conductor element. Such all item got result that is worth verified action of return trip and function through simulation, and satisfy.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.514-517
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• 2005

Microstereolithography(MSL) has evolved from the stereolithography technique, and is also based on a light-induced layer-stacking fabrication. Although integral MSL allows the manufacture of a complete layer by one irradiation only, there is a problem related with shape precision due to the light-intensity distribution of focused image. In this study, we developed the integral MSL apparatus using Digital Micromirror Device ($DMD^{TM})$, Texas Instruments) as dynamic pattern generator. It is composed of Xenon-Mecury lamp, optical devices, pattern generator, precision stage, controllers and the control program. Also, we have studied curing depth and width of photocurable resin according to the change of exposure energy.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2253-2261
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• 1999

ACK generates optimized code using the string pattern matching technique in pattern table generator and peephole optimizer. But string pattern matching method is not effective due to the many comparative actions in pattern selection. We designed and implemented the EM intermediate code optimizer using tree pattern matching algorithm composed of EM tree generator, optimization pattern table generator and tree pattern matcher. Tree pattern matching algorithm practices the pattern matching that centering around root node with refer to the pattern table, with traversing the EM tree by top-down method. As a result, compare to ACK string pattern matching methods, we found that the optimized code effected to pattern selection time, and contributed to improved the pattern selection time by about 10.8%.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.99-104
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• 1998

In this paper I designed test pattern generator which will be completely detected the faults of multi-stage Logic Circuit. 1 generated this pattern using the test pattern generation Logic Circuit. The generated test patterns compared with the exhausted testing was decreased pattern. This test pattern generator will detect the all single stuck-at faults in the multi-stage Logic Circuit. The choice of which of the many I.C testing methods to use can have a effect on the success or failure of the fault detected. One of the most important considerations is cost and designed test pattern generator is very low cost type.

• The KIPS Transactions:PartD
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• v.11D no.4
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• pp.907-916
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• 2004

The present code generation system, developing based on single system, Is not easy for developers or maintenance men to share pattern design information in distribution environment. So in this paper, we design and implement XML as basis of web environment, and JiKU/XML object-oriented code generator using pattern design. We use UML to change pattern design to XML code, and create code, suitable to PIML command, to generate design information designed by UML into XML code. This JiKU/XML Object-oriented Code Generator makes 10-step codes, and can be easily applied to web environment. It complements the disadvantage of present generator, F77/J++, and makes standardization of design because it uses UML and design pattern information. We compare it with present system by implement Eases, and as a result, generator suggested in this study gives more effective function.