• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.73-81
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• 2003

The construction industry has been experiencing a major challenge in its work force, 'the shortage of skilled craft workers.' This problem has been caused by several factors such as the poor image of the construction industry, lack of training and education, unclear career path, declining wages, and changing work force demographics. A 'step-change' approach called the 'Two-Tier Work Force Strategy' has been proposed by the Center for Construction Industry Studies (CCIS) to deal with the work force related issues in a radical way. It is composed of two separate strategies, Tier I and II. The Tier I strategy uses less skilled and task trained craft workers, and has a larger administrative site management team than the Tier II strategy. The Tier II strategy utilizes fewer, better-educated, and higher skilled workers who perform some lower-management functions in addition to craft functions. They are paid more, but produce more through higher skills, stay on the job longer through multi-skilling, and deliver improved project performance in safety, quality, schedule, and cost The Two-Tier Work Force Strategy has the potential to resolve the current work force problems and foster a better work force environment in the future.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.