The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
권호 표지
DOI QR코드

DOI QR Code

A Model-based Methodology for Application Specific Energy Efficient Data path Design Using FPGAs

FPGA에서 에너지 효율이 높은 데이터 경로 구성을 위한 계층적 설계 방법

  • Published : 2005.10.01
Download PDF
⟨ Previous Next ⟩

Abstract

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

본 논문은 ffGA상에서 에너지 효율이 높은 데이터 경로 설계 방법론을 제안한다. 에너지, 처리시간, 그리고 면적간의 트레이드오프를 이해하기 위하여, 도메인 특성 모델링, coarse-grained 성능평가, 설계공간 조사, 그리고 로우-레벨 시뮬레이션 과정들을 통합한다. 도메인 특성 모델링 기술은 도메인의 특성에 따른 시스템 전체의 에너지 모에 영향을 미치는 여러 가지 구성요소와 파라미터들을 식별함으로써 하이-레벨 모델을 명시한다. 도메인이란 주어진 어플리케이션 커널의 알고리즘에 대응하는 아키텍쳐 패밀리이다. 하이-레벨 모델 또한 에너지, 처리시간 그리고 면적을 예측하는 함수들로 구성되어 트레이드오프 분석을 용이하게 한다. 설계 공간 조사(DSE)는 도메인에 명시된 설계 공간을 분석하여 설계 셋을 선택하도록 한다. 로우-레벨 시뮬레이션은 설계 공간 조사(DSE)에 의해 선택된 설계와 최종 선택된 설계의 정확한 성능평가를 위하여 사용된다. 본 논문에서 제안한 설계 방법은 매트릭스 곱셈에 대응하는 알고리즘과 아키텍쳐 패밀리를 사용한다. 제안된 방법에 의해 검증된 설계는 에너지, 처리시간과 면적간의 트레이드오프를 보인다. 제안된 설계 방법의 효율성을 보이기 위하여 Xilinx에서 제공되는 매트릭스 곱셈 커널과 비교하였다. 성능 비교 메트릭으로 평균 전력 밀도(E/AT)와 에너지 대 (면적 x 처리시간)비를 사용하였다. 다양한 문제의 크기에 대하여 Xilinx설계들과 비교하였을 때 제안한 설계 방법이 전력밀도(E/AT)에서 평균 $25\%$우수하였다. 또한 본 논문에 제안한 설계의 방법을 MILAN 프레임워크를 이용하여 구현하였다.

Keywords

References

  1. A. Agrawal, A. Bakshi, J. Davis, B. Eames, A. Ledeczi, S. Mohanty, V. Mathur, S. Neema, G. Nordstrom, V. Prasanna, C. Raghavendra, M. Singh, 'MILAN: A Model Based Integrated Simulation for Design of Embedded Systems,' Language Compilers and Tools for Embedded Systems, 2001
  2. K. Bondalpati and V. K. Prasanna, 'Loop Pipelining and Optimization for Reconfigurable Architectures,' Reconfigurable Architectures Workshop(RAW), May, 2000
  3. S. Choi, S. Mohanty, J. Jang, and V. K. Prasanna, 'Domain-Specific Modeling for Rapid System-Level Energy Estimation of Reconfigurable Architectures,' Intl. Conference on Engineering of Reconfigurable Systems and Algorithms, 2002
  4. A. Dandalis, and V. K. Prasanna, 'Signal Processing using Reconfigurable System-on-Chip Platforms,' International Conference on Engineering of Reconfigurable Systems and Algorithms, June, 2001
  5. J. A. B. Fortes, K. S. Fu, and B. Wah, ${\ll}$Systematic Approaches to the Design of Algorithmically Specified Systolic Arrays${\gg}$, International Conference on Acoustics, Signal and Speech Processing, 1985 https://doi.org/10.1109/ICASSP.1985.1168513
  6. A. Garcia, W. Burleson, and J. L. Danger, 'Power Modeling in FPGAs', 9th International Conference on Field Programmable Logic and Applications, 1999
  7. J. Jang, S. Choi, and V. K. Prasanna, 'Energy-Efficient Matrix Multiplication on FPGAs,' FPL 2002, Lecture Notes in Computer Science, pp.534-544
  8. D. Kumar and K. Parhi, 'Performance Trade-off of DCT architectures in Xilinx FPGAs,' The 33rd Asilomar Conference on Signals, and Computers, 1999 https://doi.org/10.1109/ACSSC.1999.832396
  9. V. Kumar, A. Grama, A. Gupta, and G. Karypis, 'Introduction to Parallel Computing: Design and Analysis of Algorithms,' Benjamin Cummings, November, 1993
  10. S. Lei and K. Yao, 'Efficient Systolic Array Implementations of Digital Filtering,' IEEE International Symposium on Circuits and Systems, 1989
  11. W. Luk, N. Shirazi, and PY.K. Cheung, 'Modeling and Optimizing Run-time Reconfigurable Systems,' IEEE Symposium on FPGAs for Custom Computing Machines, 1996 https://doi.org/10.1109/FPGA.1996.564815
  12. Model-based Integrated Simulation, http://milan.usc.edu
  13. S. Mohanty, V.K. Prasanna, S. Neema, and J. Davis, 'Rapid Design Space Exploration of Heterogeneous Embedded Systems using Symbolic Serach and Multi-Granular Simulation,' Language Compilers and Tools for Embedded Systems, 2002 https://doi.org/10.1145/513829.513835
  14. M. Nemani and F. N. Najm, 'High-level Area and Power Estimation for VLSI Circuits,' IEEE/ACM International Conference on Computer-Aided Design, 1997 https://doi.org/10.1109/ICCAD.1997.643385
  15. V. K. Prasanna Kumar and Y. Tsai, 'On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication,' IEEE Transactions on Computers, Vol.40, No.6, 1991 https://doi.org/10.1109/12.90254
  16. A. Raghunathan, N.K. Jha, and S. Dey, 'High-level Power Analysis and Optimization,' Kluwer Academic Publishers, 1998
  17. F. G. Wolff, M. J. Knieser, D. F. 'Low Power FPGA Design Methodology,' National Aerospace and Electronics Conference, 2000 https://doi.org/10.1109/NAECON.2000.894960
  18. Xilinx Application Note: Vcrtcx-Il/Vertex-Il Pro Series and Xilinx ISE 4.1 Design Environment, http://www.xilinx.com
  19. Sumit Mohanty and Viktor K. Prasanna, 'Energy Efficient Application Design using FPGAs,' FPGA and Programmable Logic Journal, October, 2004
  20. Jingzhao Ou and Viktor K. Prasanna, 'A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs,' International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA), June, 2004