• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.775-778
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• 1998

근래에 들어 컴퓨터 기술은 멀티미디어 기수의 발달과 더불어 그에 따른 데이터량의 증가로 인해 데이터를 처리, 전송, 저장하는 모든 부문에서의 고속, 대용량화를 요구하고 있다. 이 중에서 특히 저장장치 부문은 응용 프로그램이 대형화되고 멀티미디어화에 따른 데이터량이 크게 증가하는 추세에 있기 때문에 지속적인 용량 증가가 요구되고 있다. 이런 상황에서 주목을 받고 있는 것이 신호처리 방식을 개선하여 저장장치의 기록 밀도를 향상시키는 기술의 하나인 partial response maximum likelihood (PRML) 기술이다. PRML 방식은 HDD 나 광 디스크로부터 데이터를 읽어낼때의 신호처리 기술 중의 ㅎ나로 신호간 간섭을 허용하여 데이터 속도를 증가시키고, 신호를 재생할 때 신호간 간섭을 보상하여 원래 신호를 복원해 내는 기술이다. 이를 이용하면 기존의 기록방식에 비해 기록밀도를 20-50% 정도 높일 수 있다.〔1〕〔2〕

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.244-247
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• 2000

This paper deals with methods for partial response maximum-likelihood (PRML) detection and crosstalk cancellation. In accrodance with the demand for increased recording density, 20 gigabyte (Gbyte) digital versatile disk (DVD) ROM channel is considered. Channel is modelled to be close to real optical channel using DIFFRACT$\^$TM/. After comparing the spectral characteristics of various PR polynomials, P(D)=1＋D＋D$^2$＋D$^3$is proposed as a target PR. The performance of the system is illustrated under the condition that the readout signal is degraded by crosstalk, radial tilt and nonlinear distortions in optics. The experimental results show that crosstalk and nonlinear distortions degrade performance by about 2dB, respectively. We also show that when radial tilt is added to the crosstalk, the performance degradation assumes quite significant proprotions.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.141-144
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• 2000

PRML (partial response maximum-likelihood) 과 FDTS/DF (fixed-delay tree search with decision feedback)는 기록 저장 시스템에서 준최적의 성능을 보임이 잘 알려져 있다. 그러나, 위와 같은 정보열 검출 기법은 피할 수 없는 복잡도 문제를 가지고 있다. 본 논문은 최소 run 길이 제한조건 d=2를 가진 광기록 채널을 위한 다양한 저복잡도 검출 기법을 다룬다. 우선, 결정 궤환 기법을 이용한 이산 정합 여파기 (discrete matched filter with decision feedback：DMF/DF)가 기존의 PRML로부터 유도된다. 유도된 시스템은 PRML보다 결정 궤환에 의한 성능 이득을 갖는다. 또한, 메트릭 계산을 사용하지 않는 저복잡도 FDTS/DF가 유도된다. 모의실험 결과에 의하면, 유도된 저복잡도 검출 기법들은 기록 밀도 S>=5.5에서 P(D)=1+D+D/sup 2/+D/sup 3/의 target을 갖는 PRML보다 우수한 성능을 보인다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.255-258
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• 2000

본 논문에서는 효율적인 면적의 저전력 FIR 필터를 제안한다. 제안된 필터는 6 비트 8 탭의 구조를 갖는PRML(Partial-Response Maximum Likelihood) 디스크드라이브 read channel용 FIR 필터이다 제안된 구조는 병렬연산 구조를 채택하고 있으며 네 단의 파이프라인 구조를 가지고 있다. 곱셈을 위하여 부스 알고리즘이 사용되며 압축기를 이용하여 덧셈을 수행한다. 저전력을 위해 CMOS 패스 트랜지스터를 사용하였으며 면적을 줄이기 위해 single-rail 로직을 사용하였다 제안된 구조를 0.65㎛ CMOS 공정을 이용하여 설계하였으며1.88 × 1.38㎟의 면적을 차지하였고 HSPICE 시뮬레이션 결과 3.3V의 공급전압에서 100㎒로 동작시 120㎽의 전력을 소모한다. 제안된 구조는 기존의 구조들에 비해 약 11%의 전력이 감소했으며 약 33%의 면적이 감소하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1052-1057
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• 2006

The implement the adaptive partial response maximum likelihood (PRML) detector with tilt analyzer for asymmetric high-density optical storage system. For the estimation of disc tilt, we exploit spc patterns in each data frame. Because of using the ROM table to renew the coefficients of equalizer and reference values of branches, the complexity of the hardware is reduced. The proposed PRML has been designed and verified by VerilogHDL and synthesized by the Synopsys Design Compiler with Hynix $0.35{\mu}m$ STD cell library. In the result, the total gate count is 35K, and the maximum operating frequency is 140MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.28-33
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• 2007

The front-end system having a capable of 2x reading and writing of BD-R/Ra/ROM is developed. Its readability is improved by adopting 5-tap adaptive partial response maximum likelihood (PRML) with the PR(a,b,c,d,e) type channel. Due to the proposed PRML, less than $2{\times}10^{-4}$ of the bit error rate (BER) is achieved with radial and tangential tilt margin of over${\mp}0.6{\circ}$ on 25GB disc in 2x speed. The method of an optimum Power control (OPC) for stable writing of various BD-R/RE is proposed. The developed chip contains 14-million transistors in a $60mm^2$ dies, and is fabricated in $0.18-{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.927-932
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• 2006

We Propose a partial response maximum likelihood(PRML) detection method that improves the performance of the high-density optical storage system. It concurrently adjusts the coefficient of equalizer and reference values of branches in Viterbi detector. For the estimation of asymmetric channel characteristics by the tangential tilt, we exploit sync patterns in each data frame. The simulation result shows it improves the Performance up to 4dB at 10-6 BER compared to conventional adaptive PRML.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1601-1605
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• 2004

When codeword sequence has two or less successive transitions, the performance of 4th-order partial response maximum-likelihood (PRML) detector can be improved. However, the code leads to an unacceptable loss of performance due to the low code rate. For a rate 718 code that MTR constraint (i) of each codeword is limited to 2, and j is allowed to be 3 when codewords are connected, we modified the trellis of PRML detector to combine j=2 with J=3. We confirmed that the rate 718 coded 4th-order PRML detection with combined trellis achieves the SNR gain more than 2dB compared to the rate 819 coded 4u_order PRML detection at 10-s BER in high-density longitudinal or perpendicular magnetic recording systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.581-586
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• 2010

The holographic data storage system stores multiple data pages by multiplexing. But the inter-page interference(IPI) caused by multiplexing reduces the intensity of the hologram. The simulation of the holographic storage systems has to consider the IPI. Therefore, we introduce a channel modeling that takes care of inter-page interference in the holographic data storage system. We simulate the performance of PRML detection on the hologrpahic data storage system with IPI modeling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.115-124
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• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.