• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.3
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• pp.504-514
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• 1994

Combinational automatic test pattern generators (CATPG) have already been commercialized because their algorithms are well known and practical, while sequential automatic test pattern generators(SATPG) have been regarded as impractical because they are computationally complex. A technique to use CATPG instead of SATPG for test generation of sequential circuits is proposed. Redesign of seauential circuits such as Level Sensitive Scan Design (LSSD) is inevitable to use CATPG. Various partial scan techniques has been proposed to avoid full scan such as LSSD. It ha sbeen reported that SATPG is required to use partial scan techniques. We propose a technique to use CATPG for a new partial scan technique, and propose a new CATPG algorithm for the partially scanned circuits. The partial scan technique can be another choice of design for testability because it is computationally advantageous.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.1-15
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• 1998

In this paper, we propose a partial scan test method which can be applied to large VLSI designs. In this method, it is not necessary to hold neither scanned nor unscanned flip-flops during scan in, test application,or scan out. This test method requires almost identical design for testability modification and test wave form when compared to the full scan test method, and the method is applicable to large VLSI chips. The well known FAN algorithm has been modified to devise to sequential ATPG algorithm which is effective for the proposed test method. In addition, a partial scan algorithm which is effective for the proposed test method. In addition, a partial algorithm determined a maximal set of flip-flops which gives high fault coverage when they are unselected. The experimental resutls show that the proposed method allow as large as 20% flip-flops to remain unscanned without much decrease in the full scan fault coverage.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.49-58
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• 1998

In this paper, we report new algorithms to select scan flip-flops for the no holding partial scan test method. The no holding partial scan test method is identical to the full scan test method except that some flip-flops are left unscanned. This test method does not hold scanned or unscanned flip-flops while shifting in test vectors, or applying them, or shifting out test results. The proposed algorithm allows a large number of flip-flops to be left unscanned while maintaining almost the complete full scan fault coverage.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Journal of Mechanical Science and Technology
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• v.20 no.10
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• pp.1691-1701
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• 2006

The scan type magnetic camera is proposed to improve the limited spatial resolution due to the size of the packaged magnetic sensor. An image of the scan type magnetic camera, ${\partial}B/{\partial}x$ image, is useful for extracting the crack information of a specimen under a large inclined mag netic field distribution due to the poles of magnetizer. The ${\partial}B/{\partial}x$ images of the cracks of different shapes and sizes are calculated by using the improved dipole model proposed in this paper. The improved dipole model uses small divided dipole models, the rotation and relocation of each dipole model and the principle of superposition. Also for a low carbon steel specimen, the experimental results of nondestructive testing obtained by using multiple cracks are compared with the modeling results to verify the effectiveness of ${\partial}B/{\partial}x$ modeling. The improved dipole model can be used to simulate the LMF and ${\partial}B/{\partial}x$ image of a specimen with complex cracks, and to evaluate the cracks quantitatively using magnetic flux leakage testing.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.4
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• pp.210-215
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• 2004

This paper proposes an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, a Boolean function is derived, whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, it is possible to exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. The algorithm proposed in this paper is the first to obtain the MFVS solutions for many benchmark circuits.

• Journal of the Korean Society for Nondestructive Testing
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• v.36 no.5
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• pp.353-362
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• 2016

Thermal barrier coating (TBC) is an essential element consisting of a super-alloy base and ceramic coating designed to achieve long operational time under a high temperature and pressure environment. However, the top coat of TBC can be delaminated at certain temperatures with long operation time. As the delamination of TBC is directly related to the blade damage, the coupling status of the TBC should be assured for reliable operation. Conventional studies of nondestructive evaluation have been made for detecting generation of thermally grown oxide (TGO) or qualitatively evaluating delamination in TBC. In this study, the ultrasonic C-scan method was developed to obtain the damage map inside TBC by estimating the delamination in a quantitative way. All specimens were isothermally degraded at $1,100^{\circ}C$ with different time, having different partial delamination area. To detect partial delamination in TBC, the C-scan was performed by a single transducer using pulse-echo method with normal incidence. Partial delamination coefficients of 1 mm to 6 mm were derived by the proportion of the surface reflection signal and flaw signal which were theoretical signals using Rogers-Van Buren and Kim's equations. Using the partial delamination coefficients, the partial delamination maps were obtained. Regardless of the partial delamination coefficient, partial delamination area was increased when degradation time was increased in TBC. In addition, a decrease in partial delamination area in each TBC specimen was observed when the partial delamination coefficient was increased. From the portion of the partial delamination maps, the criterion for delamination was derived.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.7-13
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• 1997

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns sifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can e applied by scan shifting and then pulsing a system clock like the full scan but with much les scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.278-281
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• 2009

In this paper, we propose a fast partial distortion algorithm using normalized dithering matching scan to get uniform distribution of partial distortion which can reduce only unnecessary computation significantly. Our algorithm is based on normalized dithering order matching scan and calibration of threshold error using LOG value for each sub-block continuously for efficient elimination of unlike candidate blocks while keeping the same prediction quality compared with the full search algorithm. Our algorithm reduces about 60% of computations for block matching error compared with conventional PDE (partial distortion elimination) algorithm without any prediction quality, and our algorithm will be useful to real-time video coding applications using MPEG-4 AVC or MPEG-2.