• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.499-501
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• 2008

본 논문은 공진요소를 포함한 고전압 플라이백 컨버터의 설계 절차를 제시하는 것으로써, 고압 플라이백 컨버터 설계 시 기존 플라이백 컨버터의 Power Stage 설계 식을 적용하였을 때 원하는 출력 전압을 얻지 못한다. 고전압을 발생시키기 위한 고전압 플라이백 변압기는 2차 측의 많은 권선수와 높은 전압 때문에 기생 커패시턴스(parasitic capacitance)가 매우 크고, 과도상태에서 컨버터 전류 및 전압의 기생 공진(parasitic resonance)이 심각하게 발생한다. 이러한 공진요소를 고려하여 고전압 플라이백 컨버터의 특성을 해석하고 설계 절차를 제시한다. 이를 통해 고전압 플라이백 컨버터의 소형화 및 경량화를 도모하고, 고압 전원장치의 기술 축적을 위해 연구되었다. 제안된 회로의 동작원리를 설명하고, 타당성을 실험을 통하여 검증한다.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• ETRI Journal
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• v.41 no.6
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• pp.715-730
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• 2019

We propose a switched beam-forming antenna that satisfies not only ultra-wideband characteristics but also beam-forming in the WLAN frequency band using an ultra-wideband antenna and passive parasitic elements applying a broadband optimal reactance load algorithm. We design a power and phase estimation function and an error correction function by re-analyzing and normalizing all the components of the parasitic array using control system engineering. The proposed antenna is compared with an antenna with a pin diode and reactance load value, respectively. The pin diode is located between the passive parasitic elements and ground plane. An antenna beam can be formed in eight directions according to the pin diode ON (reflector)/OFF (director) state. The antenna with a reactance load value achieves a better VSWR and gain than the antenna with a pin diode. We confirm that a beam is formed in eight directions owing to the RF switch operation, and the measured peak gain is 7 dBi at 2.45 GHz and 10 dBi at 5.8 GHz.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.11
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• pp.48-53
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• 2012

In this paper designed J-class amplifier that have high efficiency using parasitic of pHEMT. Measured results of the designed J-class amplifier is maxmum output power of 31.5dBm and gain of 16.5dB, minimum output power of 29.8dBm. when input power 15dBm. Maxmum drain efficiency is 76.2% at 2.95GHz, maxmum drain efficiency is 61%. The J-class amplifier has average gain of 15.35dB and average efficiency of 35%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.85-91
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• 2008

A Boost Power Factor Correction (PFC) Converter employing Zero Voltage Switching (ZVS) based Compound Active Clamping (CAC) technique is presented in this paper. An Electro Magnetic Interference (EMI) Filer is connected at the line side of the proposed converter to suppress Electro Magnetic Interference. The proposed converter can effectively reduce the losses caused by diode reverse recovery. Both the main switch and the auxiliary switch can achieve soft switching i.e. ZVS under certain condition. The parasitic oscillation caused by the parasitic capacitance of the boost diode is eliminated. The voltage on the main switch, the auxiliary switch and the boost diode are clamped. The principle of operation, design and simulation results are presented here. A prototype of the proposed converter is built and tested for low input voltage i.e. 15V AC supply and the experimental results are obtained. The power factor at the line side of the converter and the converter efficiency are improved using the proposed technique.

• Proceedings of the KIEE Conference
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• 2006.07b
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• pp.1065-1066
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• 2006

The multi-resonant converter minimizes the parasitic oscillations using the resonant tank circuit absorbed parasitic reactances in a converter. So the converter can be operated at a high frequency and it provides a high efficiency because the switching power losses are reduced effectively. However, the high resonant voltage stress of semiconductors leads to the conduction loss. In this paper, it is proposed the novel flyback multi-resonant converter. The converter input is divided by two series input capacitors. And also the resonant stress is reduced to 2-3 times input voltage without any complexity and it provides the various circuit schemes in lots of applications. The proposed converters are verified through simulation and experiment.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.347-349
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• 2013

This paper describes analysis and calculation of line frequency ripple current according to output capacitor value and effects of LED connection in the single stage flyback converter with high power factor. The low frequency output ripple current delivered from single stage converter has been analyzed in detail and the method evaluating parasitic resistance included in LED has been provided. In order to verify the equation derived in this paper, the single stage flyback converter has been designed with constant output current regulation with DCM operation. Experiments were conducted with different LED load structures to analyze the effect of LED parasitic resistance on output ripple current. As test results, the calculation can provide guide line to select capacitor values depending on output ripple current and LED characteristics.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.1
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• pp.56-61
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• 2019

In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a $1{\mu}F$ parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.217-221
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• 2001

This paper presents a new prototype of soft-switching DC-DC power converter with a high frequency transformer link which has two active power controlled switches in full bridge rectifier with capacitor input type smoothing filter. In this DC-DC converter, ZVS of the inverter in transformer primary side and ZCS of active rectifier area in secondary side can be completely achieved by taking advantage of parasitic inductor component of high-frequency transformer and loss less snubbing capacitors. Its operation principle and salient features are described. The steady-state operating characteristics of the proposed DC-DC power converter are illustrated and discussed on the basis of the simulation results in addition to the experimental ones obtained by 2kw-40kHz power converter breadboard set up.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.97-101
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• 2003

In this paper, we propose a new diagnosis method of DC/UC converter aging. The method is based on parasitic resister change with aging process. we apply to on-line diagnosis of DC/DC converter because of observing not a device but a system. We present the mathematical analysis and experimental study.