• Journal of Korean Institute of Industrial Engineers
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• v.1 no.2
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• pp.51-56
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• 1975

A computer program for computing complex system reliability is described. The program is composed of three phases : Phase I program reduces all series, parallel and series-parallel components and subsequently obtains an irreducible non-series-parallel system. Phase II program enumerates all the possible paths from the source to the sink of the graph. Phase III program then computes system reliability based on the information obtained by the Phase II program. The program is based on a modified version of the algorithm published in [6]. An example of the use of the computer program is given.

• International Journal of Internet, Broadcasting and Communication
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• v.11 no.3
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• pp.1-7
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• 2019

Previously, parallel computing was mainly used in areas requiring high computing performance, but nowadays, multicore CPUs and GPUs have become widespread, and parallel programming advantages can be obtained even in a PC environment. Various parallel programming frameworks using multicore CPUs such as OpenMP and PPL have been announced. Nvidia and AMD have developed parallel programming platforms and APIs for program developers to take advantage of multicore GPUs on their graphics cards. In this paper, we develop digital image transformation programs that runs on each of the major parallel programming frameworks, and measure the execution time. We analyze the characteristics of each framework through the execution time comparison. Also a constant K indicating the ratio of program execution time between different parallel computing environments is presented. Using this, it is possible to predict rough execution time without implementing a parallel program.

• Electronics and Telecommunications Trends
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• v.9 no.4
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• pp.9-21
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• 1994

Wide variety of the architectural complexity of parallel computer often makes it difficult to develop efficient programs for them. One of approaches to improve this difficulty is to program in familiar sequential languages such as Fortran or C and to parallelize sequential programs into equivalent parallel programs automatically. This paper presents an organization of parallelizing compiler which transforms sequential programs into equivalent parallel programs. The parallelizer consists mainly of syntax analysis, control and data flow analysis, program transformation, and parallel code generation. In particular, the program restructuring in this parallelizer maximizes loop parallelism.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.284-289
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• 2002

In this paper, we develop a six-axes machining center tool(MCT) and CAD/CAM system based RAD Tool Program. The MCT consists of two mechanical parts, i.e., a X-Y-Z Cartesian coordinate typed MCT and a parallel-typed tilting table. Kinematics and singularity are accomplished to design the parallel-typed tilting table, and RAD Tool Program Is developed for the six-axes MCT, which requires the commands of position as well as orientation for machining of complex shape. In RAD Tool, the CAD/CAM system has a tool path generator, NC code generator and a graphic simulator. This paper designs the parallel-typed tilting table to meet the desired specification and presents the results of CAD/CAM system based RAD Tool Program.

• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.69-81
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• 2001

This paper describes a parallel programming environment to help programmer to write parallel programs. Parallel program must be write according to the character of the various hardware or program. So it is difficult for the programs to write the parallel programmer. In this paper, we propose and implement a parallel programming environment using graph type intermediate representation form, and graph user interface is provided for programmer to get parallel programs easily, This parallel environment supports special functions using graph type intermediate representation form. The special functions involve program editing. data dependence analysis, loop transformation. CFG, PDG, HTG. This parallel environment helps users make parallelism and optimization easy through showing the intermediate code with graph.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.253-260
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• 2001

It is important to detect races for debugging shared-memoy parallel programs, because the races cause unintended nondeterministic program execution. Previous on-the-fly techniques to detect races can not guarantee the first race detection in nested parallel programs. Detecting the first race is important for debugging parallel programs, since the removal of the first race may make the next occurred races disappear. In this paper, we presents an on-the-fly detection technique to detect all of the first races through the reexecution of the debugged programs. We assume that the debugged parallel program may have one-way nested parallel programs. The number of reexecution is at the least the nesting depth of the program in the worst case. The space complexity is O(VT) and the time complexity to detect race in each access of access history is O(T), where V is number of shared variables and T is the maximum parallelism of the program. This efficiency of our technique in each execution is the same with the previous on-the-fly detection techniques. Therefore, this technique makes debugging parallel programs more effective and practical.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1997-2012
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• 1998

It is necessary to find out the parallelism in tlle sequential Java program to execute it on the parallel machine. The loop is a fundamental source to exploit parallelism as it process a large portion of total execution time in sequential Java program on the parallel machine. However, a complete parallel execution can hardly be achieved due to data dependence. This paper proposes the method of exploiting the implicit parallelism by structuring a dependence graph through the analysis of data dependence in the existing Java programming language having a nested loop structure. The parallel code generation method through the restructuring compiler and also the translation method of Java source program into multithread statement. which is supported by the Java programming language itself, are proposed here. The perforance evaluatlun of the program translaed into the thread statement is conducted using the trip cunt of loop and the trip Count of luop and the thread count as parameters The resttucturing compiler provides efficient way of exploiting parallelism by reducing manual overhead conveliing sequential Java program into parallel code. The execution time for the Java program as a result can be reduced un the parallel machine.

• Journal of Korea Multimedia Society
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• v.4 no.6
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• pp.579-587
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• 2001

In this paper, we design and implement a parallel programming environment using graphicial user interface. Parallel program must be written according to the characters of various hardwares or programs. So it is difficult to write the parallel program. In this paper, we design and implement a parallel programming environment which solved this problem. The traditional parallel compiler provides the parallel information in the text environment. But this paper provides the parallel information using graphicial user interface so that the user may use it more easily. This parallel environment provide functions such as, data dependence analysis, CFG, HTF, and loop transformation.

• Journal of Internet Computing and Services
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• v.12 no.3
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• pp.131-137
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• 2011

GPUs were originally designed for graphic processing, and GPGPUs are general-purpose GPUs for numerical computation with high performance and low electric power. In this paper, we implemented the parallel LU factorization program for GPGPUs. In CUDA, which is computational environment for Nvidia GPGPUs, domains are divided into blocks, and multi-threads compute each sub-blocks Simultaneously. In LU factorization program, computation order should be artificially decided due to the data dependence. To resolve the data dependancy, we suggested a parallel LU program for GPGPUs, and also explained parallel reduction algorithm for partial pivoting of LU factorization. We finally present performance analysis to show efficiency of the parallel LU factorization program based on multi-threads on GPGPUs.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1997.10a
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• pp.166-169
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• 1997

For parallel processing, the compiler partitions a loaded program into a set of tasks and makes a schedule for the tasks that will minimize parallel processing time for the loaded program. Building an optimal schedule for a given set of partitioned tasks of a program has known to be NP-complete. In this paper we introduce a GA(Genetic Algorithm)-based scheduling method in which a chromosome consists of two parts of a string which decide the number and order of tasks on each processor. An additional computation is used for feasibility constraint in the chromosome. By granularity theory, a partitioned program is categorized into coarse-grain or fine-grain types. There exist good heuristic algorithms for coarse-grain type partitioning. We suggested another GA adaptive to the coarse-grain type partitioning. The infeasibility of chromosome is overcome by the encoding and operators. The number of processors are decided while the GA find the minimum parallel processing time.