• Title/Summary/Keyword: Parallel processing model

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Range Detection of Wa/Kwa Parallel Noun Phrase using a Probabilistic Model and Modification Information (확률모형과 수식정보를 이용한 와/과 병렬사구 범위결정)

  • Choi, Yong-Seok;Shin, Ji-Ae;Choi, Key-Sun
    • Journal of KIISE:Software and Applications
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    • v.35 no.2
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    • pp.128-136
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    • 2008
  • Recognition of parallel structure at early stage of sentence parsing can reduce the complexity of parsing. In this paper, we propose an unsupervised language-independent probabilistic model for recongition of parallel noun structures. The proposed model is based on the idea of swapping constituents, which replies the properties of symmetry (two or more identical constituents are repeated) and of reversibility (the order of constituents is inter-changeable) in parallel structures. The non-symmetric patterns that cannot be captured by the general symmetry rule are resolved additionally by the modifier information. In particular this paper shows how the proposed model is applied to recognize Korean parallel noun phrases connected by "wa/kwa" particle. Our model is compared with other models including supervised models and performs better on recongition of parallel noun phrases.

Algorithmic GPGPU Memory Optimization

  • Jang, Byunghyun;Choi, Minsu;Kim, Kyung Ki
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.391-406
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    • 2014
  • The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

Energy-efficient Routing in MIMO-based Mobile Ad hoc Networks with Multiplexing and Diversity Gains

  • Shen, Hu;Lv, Shaohe;Wang, Xiaodong;Zhou, Xingming
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.2
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    • pp.700-713
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    • 2015
  • It is critical to design energy-efficient routing protocols for battery-limited mobile ad hoc networks, especially in which the energy-consuming MIMO techniques are employed. However, there are several challenges in such a design: first, it is difficult to characterize the energy consumption of a MIMO-based link; second, without a careful design, the broadcasted RREP packets, which are used in most energy-efficient routing protocols, could flood over the networks, and the destination node cannot decide when to reply the communication request; third, due to node mobility and persistent channel degradation, the selected route paths would break down frequently and hence the protocol overhead is increased further. To address these issues, in this paper, a novel Greedy Energy-Efficient Routing (GEER) protocol is proposed: (a) a generalized energy consumption model for the MIMO-based link, considering the trade-off between multiplexing and diversity gains, is derived to minimize link energy consumption and obtain the optimal transmit model; (b) a simple greedy route discovery algorithm and a novel adaptive reply strategy are adopted to speed up path setup with a reduced establishment overhead; (c) a lightweight route maintenance mechanism is introduced to adaptively rebuild the broken links. Extensive simulation results show that, in comparison with the conventional solutions, the proposed GEER protocol can significantly reduce the energy consumption by up to 68.74%.

Parallelization of A Load balancing Algorithm for Parallel Computations (병렬계산을 위한 부하분산 알고리즘의 병렬화)

  • In-Jae Hwang
    • Journal of the Institute of Convergence Signal Processing
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    • v.5 no.3
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    • pp.236-242
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    • 2004
  • In this paper, we propose an approach to parallelize a load balancing algorithm that was shown to be very effective in distributing workload for parallel computations. Load balancing algorithms are required in executing parallel program efficiently As a parallel computation model, we used dynamically growing tree structure that can be found in many application problems. The load balancing algorithm tries to balance the workload among processors while keeping the communication cost under certain limit. We show how the load balancing algorithm is effectively parallelized on mesh and hypercube interconnection networks, and analyzed the time complexity for each case to show that parallel algorithm actually reduced the various overhead.

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A Ray-Tracing Algorithm Based On Processor Farm Model (프로세서 farm 모델을 이용한 광추적 알고리듬)

  • Lee, Hyo Jong
    • Journal of the Korea Computer Graphics Society
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    • v.2 no.1
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    • pp.24-30
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    • 1996
  • The ray tracing method, which is one of many photorealistic rendering techniques, requires heavy computational processing to synthesize images. Parallel processing can be used to reduce the computational processing time. A parallel algorithm for the ray tracing has been implemented and executed for various images on transputer systems. In order to develop a scalable parallel algorithm, a processor farming technique has been exploited. Since each image is divided and distributed to each farming processor, the scalability of the parallel system and load balancing are achieved naturally in the proposed algorithm. Efficiency of the parallel algorithm is obtained up to 95% for nine processors. However, the best size of a distributed task is much higher in simple images due to less computational requirement for every pixel. Efficiency degradation is observed for large granularity tasks because of load unbalancing caused by the large task. Overall, transputer systems behave as good scalable parallel processing system with respect to the cost-performance ratio.

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An Embedding of Multiple Edge-Disjoint Hamiltonian Cycles on Enhanced Pyramid Graphs

  • Chang, Jung-Hwan
    • Journal of Information Processing Systems
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    • v.7 no.1
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    • pp.75-84
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    • 2011
  • The enhanced pyramid graph was recently proposed as an interconnection network model in parallel processing for maximizing regularity in pyramid networks. We prove that there are two edge-disjoint Hamiltonian cycles in the enhanced pyramid networks. This investigation demonstrates its superior property in edge fault tolerance. This result is optimal in the sense that the minimum degree of the graph is only four.

Parallel Computing of Large Scale FE Model based on Explicit Lagrangian FEM (외연 Lagrangian 유한요소법 기반의 대규모 유한요소 모델 병렬처리)

  • 백승훈;김승조;이민형
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.34 no.8
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    • pp.33-40
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    • 2006
  • A parallel computing strategy for finite element(FE) processing is described and implemented in nonlinear explicit FE code and its parallel performances are evaluated. A self-made linux-cluster supercomputer with 520 CPUs is used as a bench mark test bed. It is observed that speed-up is increased almost idealy even up to 256 CPUs for a large scale model. A communication over head and its effect on the parallel performance is also examined. Parallel performance is compare with the commercial code and developed code shows superior performance as the number of CPUs used are increased.

Performance Analysis of Parallel Database Machine Architectures (병렬 데이타베이스 컴퓨터 구조의 성능 분석)

  • Lee, Yong-Kyu
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.4
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    • pp.873-882
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    • 1998
  • The parallel database machine approach is currently widely and successfully used. There are four major architectures which are used in this approach: shared-nothing architecture, shared-evertying architecture, shared-disk architecture, and hybrid architecture. In this paper, we use an analytical model to evaluate the performance of these database machine architectures. We define an abstract model for each type of database machine design to obtain performance equatons describing the execution times with respect to the hybrid hash join poeration. Using the performance equations, we evaluate the execution times of the various database machine design models.

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Research on parallelization mechanism of inductively coupled plasma for large area plasma source

  • Lee, Jang-Jae;Kim, Si-Jun;Kim, Gwang-Gi;Lee, Ba-Da;Lee, Yeong-Seok;Yeom, Hui-Jung;Kim, Dae-Ung;Yu, Sin-Jae
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.183-183
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    • 2016
  • Inductively coupled plasma having the high-density is often used for high productivity in the plasma processing. In large area processing, the plasma can be generated by using the multi-pole connected in parallel. However, in case of this, the power cannot transfer to plasma uniformly. To address the problem, we studied the mechanism of inductively coupled plasma connected in parallel by using transformer model. We also studied about the change of the plasma parameters over the time through the power balance equation and particle balance equation.

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Real Time Implementittion of Time Varying Nonstationary Signal Identifier and Its Application to Muscle Fatigue Monitoring (비정상 시변 신호 인식기의 실시간 구현 및 근피로도 측정에의 응용)

  • Lee, Jin;Lee, Young-Seock;Kim, Sung-Hwan
    • Journal of Biomedical Engineering Research
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    • v.16 no.3
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    • pp.317-324
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    • 1995
  • A need exists for the accurate identification of time series models having time varying parameters, as is important in the case of real time identification of nonstationary EMG signal. Thls paper describes real time identification and muscle fatigue monitoring method of nonstationary EMG signal. The method is composed of the efficient identifier which estimates the autoregressive parameters of nonstationary EMG signal model, and its real time implementation by using T805 parallel processing computer. The method is verified through experiment with real EMG signals which are obtained from surface electrode. As a result, the proposed method provides a new approach for real time Implementation of muscle fatigue monitoring and the execution time is 0.894ms/sample for 1024Hz EMG signal.

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