• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.216-225
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• 2006

This paper presents a new circuit topology of DC busline switch and snubbing capacitor-assisted full-bridge soft-switching PWM inverter type DC-DC power converter with a high frequency link for low voltage large current applications as DC feeding systems, telecommunication power plants, automotive DC bus converters, plasma generator, electro plating plants, fuel cell interfaced power conditioner and arc welding power supplies. The proposed power converter circuit is based upon a voltage source-fed H type full-bridge high frequency PWM inverter with a high frequency transformer link. The conventional type high frequency inverter circuit is modified by adding a single power semiconductor switching device in series with DC rail and snubbing lossless capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge inverter arms and DC busline can achieve ZVS/ZVT turn-off and ZCS turn-on commutation operation. Therefore, the total switching losses at turn-off and turn-on switching transitions of these power semiconductor devices can be reduced even in the high switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules is selected to be 60 kHz. It is proved experimentally by the power loss analysis that the more the switching frequency increases, the more the proposed DC-DC converter can achieve high performance, lighter in weight, lower power losses and miniaturization in size as compared to the conventional hard switching one. The principle of operation, operation modes, practical and inherent effectiveness of this novel DC-DC power converter topology is proved for a low voltage and large current DC-DC power supplies of arc welder applications in industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.587-593
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• 2011

A new high power density and low cost Photovoltaic Power Conditioning System (PV PCS) with energy storage system is proposed. Its high power density and cost effectiveness can be achieved through the unification of the maximum power point tracker and battery charger/discharger. Despite of the reduced power stage, the proposed system can achieve the same performances of maximum power point tracking and battery charging/discharging as the conventional system. Moreover, the high voltage stress across the link-capacitor can be relieved through the series-connected link-capacitor with the battery. Therefore, a large number of series/parallel-connected link-capacitors can be reduced by 4-times. Especially, when the utility power failure happens, both photovoltaic and battery energies can be supplied to the load with only one power stage. Therefore, it features a simpler structure, less mass, lower cost, and fewer devices. Finally, to confirm the operation, validity, and features of the proposed system, theoretical analysis and experimental results from a single phase AC 220Vrms/1.5kW prototype are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.2043-2052
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• 1994

This paper proposes a new parallel ASIC architecture for real-time image processing to reduce inter-processing element (inter-PE) communication overhead, called a Sliding Memory Plane (SliM) Image Processor. The Slim Image Processor consists of $3\times3$ processing elements (PEs) connected by a mesh topology. With easy scalability due to the topology. a set of SliM Image Processors can form a mesh-connected SIMD parallel architecture. called the SliM Array Processor. The idea of sliding means that all pixels are slided into all neighboring PEs without interrupting PEs and without a coprocessor or a DMA controller. Since the inter-PE communication and computation occur simultaneously. the inter-PE communication overhead, significant disadvantage of existing machines greatly diminishes. Two I/O planes provide a buffering capability and reduce the date I/O overhead. In addition, using the by-passing path provides eight-way connectivity even with four links. with these salient features. SliM shows a significant performance improvement. This paper presents architectures of a PE and the SliM Image Processor, and describes the design of an instruction set.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.77-81
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• 2004

In this paper a novel line interactive UPS (Uninterruptible Power Supply) using the two 4-leg VSCs and AC line reactor is proposed. The 4-leg Voltage Source Converter(VSC) can use the DC link voltage effectively by the 3-D SVPWM method. Hence the DC battery voltage can be reduced by $15\%$ in comparison to that of the conventional line-interactive UPS system. One VSC is in parallel with the AC line reactor of the power source side, and the other is in series with the load. The parallel 4-leg voltage source inverter controls three-phase line voltage independently in order to control the line reactor current indirectly. It eliminates the neutral line current and the active ripple power of the source side using the pqr theory so that unity power factor and the sinusoidal source current can be achieved even though both the source and the load voltages have zero sequence components. The series 4-leg voltage source inverter compensates the line voltage and allows the load voltage to be balanced and harmonic-free. Both of parallel and series 4-leg voltage source inverters always act as independently controllable voltage sources, so that three-phase output voltage shows a seamless transition to the backup mode. The feasibility of the proposed UPS system has been investigated and verified through computer simulation results.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.101-104
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• 2001

Over the last few years, streaming audio and video content on Internet sites has increased at unprecedented rates. The predominant method of delivering video over the current Internet is video streaming such as SureStream or Intelligent Stream. Since each method provides the client with only one data stream from one server, it often suffers from poor qualify of pictures in the case of network link congestion. In this paper, we propose a novel method of delivering video stream based on wavelet to a client by utilizing multi-threaded parallel connections from the client to multiple servers and to provides a better way to address the scalability functionalities. The experimental results show that the video quality delivered by the proposed multithreaded stream could significantly be improved over the conventional single video stream methods.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.249-250
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• 2016

본 논문에서는 3병렬 풍력발전 시스템의 직류단 전류 리플을 저감하기 위한 인터리빙 기법을 제안한다. 병렬 구조의 풍력발전 시스템은 각 발전기 측 컨버터의 전류 고조파로 인해 직류단에 전류 리플이 발생한다. 이러한 전류 고조파들의 합과 관련된 전류 리플은 직류단 커패시터의 수명 단축 및 전체 시스템의 손실을 유발한다. 이를 방지하기 위해 3병렬 풍력발전 시스템에서의 전류 고조파를 분석하고, 전류 리플을 최소화하기 위한 최적의 인터리빙 각을 구하여 전류 리플을 저감하는 기법을 제안한다. 제안하는 기법의 타당성을 PSIM 시뮬레이션을 통해 확인한다.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.82-86
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• 2004

In this paper, a cycler system for the Lithium-Polymer battery with the large capacity of 120Ah is presented. This system is constituted as the two units for the charging and discharging. The Lithium-Polymer battery should be charged in CC and CV mode, and it is required a very high precision control of the voltage and current for the charging unit. To decrease the switching noises and harmonics, parallel operation method is adopted and utilized in the power conversion module. The discharging unit has a link AC system function to return the discharging energy of battery to AC line and has comparatively less thermal loss. These units are designed to be controlled and monitored by personal computer. The total system for the battery charging and discharging is described and presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1063-1066
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• 2002

An equivalent circuit for the superconductor flux flow transistor(SFFT) was combined with high temperature cooling device, based on the analogy between thermal and electrical variables using the high-temperature superconductor(HTS), is proposed. The device is composed of parallel weak links with a nearby magnetic control line. A model has been developed that is based on solving the equation of motion of Abrikosov vortices subject to Lorentz viscous and pinning forces as well as magnetic surface barriers. The use of thermal models the global performance of thermal cooling circuit and signal system to be checked by using electrical circuit analysis programs such as SPICE.