• Journal of Power Electronics
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• v.16 no.1
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• pp.297-309
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• 2016

Grid-connected inverters (GCIs) with an LCL output filter have the ability of attenuating high-frequency (HF) switching ripples. However, by using only grid-current control, the system is prone to resonances if it is not properly damped, and the current distortion is amplified significantly under highly distorted grid conditions. This paper proposes a synchronous reference frame equivalent proportional-integral (SRF-EPI) controller in the αβ stationary frame using the parallel virtual resistance-based active damping (PVR-AD) strategy for grid-interfaced distributed generation (DG) systems to suppress LCL resonance. Although both a proportional-resonant (PR) controller in the αβ stationary frame and a PI controller in the dq synchronous frame achieve zero steady-state error, the amplitude- and phase-frequency characteristics differ greatly from each other except for the reference tracking at the fundamental frequency. Therefore, an accurate SRF-EPI controller in the αβ stationary frame is established to achieve precise tracking accuracy. Moreover, the robustness, the harmonic rejection capability, and the influence of the control delay are investigated by the Nyquist stability criterion when the PVR-based AD method is adopted. Furthermore, grid voltage feed-forward and multiple PR controllers are integrated into the current loop to mitigate the current distortion introduced by the grid background distortion. In addition, the parameters design guidelines are presented to show the effectiveness of the proposed strategy. Finally, simulation and experimental results are provided to validate the feasibility of the proposed control approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1455-1468
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• 2016

This paper presents a grid-connected dual stator-winding induction generator (DWIG) wind power system suitable for wide wind speed ranges. The parallel connection via a unidirectional diode between dc buses of both stator-winding sides is employed in this DWIG system, which can output a high dc voltage over wide wind speed ranges. Grid-connected inverters (GCIs) do not require booster converters; hence, the efficiency of wind energy utilization increases, and the hardware topology and control strategy of GCIs are simplified. In view of the particularities of the parallel topology and the adopted generator control strategy, we propose a novel excitation-capacitor optimization solution to reduce the volume and weight of the static excitation controller. When this excitation-capacitor optimization is carried out, the maximum power tracking problem is also considered. All the problems are resolved with the combined control of the DWIG and GCI. Experimental results on the platform of a 37 kW/600 V prototype show that the proposed DWIG wind power system can output a constant dc voltage over wide rotor speed ranges for grid-connected operations and that the proposed excitation optimization scheme is effective.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.57-66
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• 1993

This research proposes a high frequency series resonant inverter consisting of equivalent half - bridge model in combination with two L-C linked full-bridge inverter circuits using MOSFET. As a output power control strategy, the sequential gate control method is applied. Also, analysis of operating MODE and state equation is described. From the computer simulation results, the inverters and devices can be shared properly voltage and current rating of the system in accordance with series and parallel operations. And it is confirmed that the proposed system has very stable performance.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1380-1391
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• 2015

This paper provides a loss analysis and comparison of high power semiconductor devices in 5MW Permanent Magnet Synchronous Generator (PMSG) Medium Voltage (MV) Wind Turbine Systems (WTSs). High power semiconductor devices of the press-pack type IGCT, module type IGBT, press-pack type IGBT, and press-pack type IEGT of both 4.5kV and 6.5kV are considered in this paper. Benchmarking is performed based on the back-to-back type 3-level Neutral Point Clamped Voltage Source Converters (3L-NPC VSCs) supplied from a grid voltage of 4160V. The feasible number of semiconductor devices in parallel is designed through a loss analysis considering both the conduction and switching losses under the operating conditions of 5MW PMSG wind turbines, particularly for application in offshore wind farms. This paper investigates the loss analysis and thermal performance of 5MW 3L-NPC wind power inverters under the operating conditions of various power factors. The loss analysis and thermal analysis are confirmed through PLECS Blockset simulations with Matlab Simulink. The comparison results show that the press-pack type IGCT has the highest efficiency including the snubber loss factor.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.639-647
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• 2007

This paper proposed the novel method that can realize the parallel coupled line(PCL) band-pass filter with directly coupled feeding structure by means of transforming the first and last PCL sections of the conventional PCL band-pass filter into K-inverters, then substituting T-type equivalence for K-inverter. The proposed method supplies simple design formulae and can considerably reduce time and efforts needed to optimize filter performance when compared to reported methods using external Q or equivalent parameters. On the basis of the proposed method, the band-pass filter using directly coupled feeding structure and having 18% fractional bandwidth was designed and fabricated. The validity of proposed method was proven by the measured result.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.327-330
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• 2001

본 논문에서는 고압 대전력 3상 유도전동기의 고정자 권선을 이용한 전압원 인버터의 병렬운전 방식을 제안한다. 현재 사용되고 있는 대부분의 4극 이상 대전력 유도전동기는 각 상의 권선이 외부에서 접근이 가능하도록 외부단자가 설치되어 있으며, 이들 외부단자를 이용하여 복수대의 전압원 인버터를 병렬운전하여 대전력 유도전동기를 구동할 수 있다. 이와 같이 고압 대전력 유도전동기를 복수 개의 전압원 인버터를 병렬 운전하여 구동할 경우, 특정 인버터의 고장발생 시 비록 구동 토크는 감소될지라도, 나머지 인버터로 시스템을 계속 구동할 수 있어 시스템의 고장대처능력을 향상시킬 수 있다. 또한 병렬 운전되고 있는 각 인버터의 스위칭 동작에 대해 서로 위상 차를 갖게 함으로서, 등가 스위칭 주파수를 증가시켜 출력 토크 리플 감소와 입력 전류 리플 감소, DC Link 커패시터의 크기 감소와 같은 좋은 특성을 얻을 수 있다. 또한 각 인버터로의 전력의 분산에 의해 시스템에서 발생하는 EMI 영향을 감소시킬 수 있다. 본 논문에서는 제안한 방식을 컴퓨터 시뮬레이션을 통해 특성을 증명하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.7
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• pp.1193-1203
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• 2016

This paper proposes a droop control scheme to compensate the unbalanced line-to-line voltage of unbalanced 3-phase load which is coupled with two inverter-based distributed generations through unequal impedance lines. Unbalanced line-to-line load voltages occur due to using single-phase loads, which brings about bad effects on the coupled inverters and the distributed generations. In order to compensate the unbalanced line-to-line voltages, a positive sequence voltage control was used for sharing the active and reactive power and a negative sequence control was used for reducing the negative sequence voltage. The feasibility of the proposed scheme was first verified by computer simulations, and then experiments with a hardware set-up built in the lab. The experimental results were compared with the simulation results to confirm the feasibility of the proposed scheme.