• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.27-34
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• 1994

Block matching motion estimation is the most widely used method for motion compensated coding of image sequences. Based on a two dimensional systolic array, VLSI architecture and implementation of the full search block matching algorithm are described in this paper. The proposed architecture improves conventional array architecture by designing efficient processing elements that can control the data prodeuced by efficient search window division method. The advantages are that 1) it allows serial input to reduce pin counts for efficient composition of local memories but performs parallel processing. 2) It is flexible and can adjust to dimensional changes of search windows with simple control logic. 3) It has no idel time during the operation. 4) It can operate in real/time for low and main level in MPEG-2 standard. 5) It has modular and regular structure and thus is sutiable for VLSI implementation.

• Journal of International Society for Simulation Surgery
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• v.3 no.1
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• pp.16-21
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• 2016

Computed tomography (CT) can completely digitize the interior and the exterior of nearly any object without any destruction. Generally, the resolution for industrial CT is below a few microns. The industrial CT scanning, however, has a limitation because it requires long measuring and processing time. Whereas, 2D X-ray imaging is fast. In this paper, we propose a novel concept of 3D non-destructive inspection technique using the advantages of both micro-CT and dual X-ray images. After registering the master object’s CT data and the sample objects’ dual X-ray images, 3D non-destructive inspection is possible by analyzing the matching results. Calculation for the registration is accelerated by parallel computing using graphics processing unit (GPU).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.3
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• pp.39-52
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• 2009

Scale Invariant Feature Transform (SIFT) is an effective algorithm in object recognition, panorama stitching, and image matching, however, due to its complexity, real time processing is difficult to achieve with software approaches. This paper proposes using a reconfigurable hardware processor with integer half kernel. The integer half kernel Gaussian reduces the Gaussian pyramid complexity in about half [] and the reconfigurable processor carries out a parallel implementation of a full search Fast SIFT algorithm. We use a low memory, fine grain single instruction stream multiple data stream (SIMD) pixel processor that is currently being developed. This implementation fully exposes the available parallelism of the SIFT algorithm process and exploits the processing and I/O capabilities of the processor which results in a system that can perform real time image and video compression. We apply this novel implementation to images and measure the effectiveness. Experimental simulation results indicate that the proposed implementation is capable of real time applications.

• Annual Conference of KIPS
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• 2007.05a
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• pp.769-772
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• 2007

공간 데이터의 효율적인 처리는 현대의 멀티미디어 데이터베이스에 있어서 대단히 중요한 역할을 하고 있다. 많은 응용분야에서 방대한 양의 공간 데이터는 보조기억장치(예: disk)에 저장이 되어 사용이 되고 공간 색인구조의 처리는 I/O에 대한 의존도가 크므로, I/O 연산의 병렬처리는 공간 색인구조의 질의반응시간을 현저하게 줄일 수 있다. 본 논문에서는 PR-tree라는 병렬형 공간 색인구조를 제안한다. PR-tree는 MXR-tree에 비해 높은 공간활용도와 빠른 처리시간을 보임으로써 공간 데이터베이스를 위한 효율적인 색인구조로 사용이 될 것으로 기대된다.

• Journal of the Korea Society for Simulation
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• v.5 no.2
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• pp.25-40
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• 1996

Modeling of systems for intensive knowledge-based processing requires a modeling methodology that makes efficient access to the information in huge data base models. The proposed level access mothodology is a modeling approach applicable to systems where data is stored in a hierarchical and modular modules of active memory cells(processor/memory pairs). It significantly reduces the effort required to create discrete event simulation models constructed in hierarchical, modular fashion for above application. Level access mothodology achieves parallel access to models within the modular, hierarchical modules(clusters) by broadcasting the desired operations(e.g. querying information, storing data and so on) to all the cells below a certain desired hierarchical level. Level access methodology exploits the capabilities of object-oriented programming to provide a flexible communication paradigm that combines port-to-port coupling with name-directed massaging. Several examples are given to illustrate the utility of the methodology.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.1-10
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• 1994

In most application programs, loops usually contain most of the computation in a program and are the most improtant source of parallelism. When loops are executed on multiprocessors, the cross iteration data dependences need to be enforced by synchronization between processors. In this paper, we propose a new synchronization scheme(Free/Hold) for reducing overgeads occured by synchronization variables in data oriented scheme and delay of time occured by synchronization instruction in statement oriented scheme. The Free/Hold mechanism enforces the correct execution order by inserting synchronization instruction between each instance with data dependence relationship using the RD(Real dependence Distance). We also present an algorithm for removing unnecessary dependences in one-to-many dependences.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.453-455
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• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.

• Water for future
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• v.29 no.4
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• pp.109-118
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• 1996

The neural network is a mathematical model of theorized brain activity which attempts to exploit the parallel local processing and distributed storage properties. The neural metwork is a good model to be applied for the classification problem, large combinatorial optimization and nonlinear mapping. A multi-layer neural network is constructed to predict rainfall. The network learns continuourvalued input and output data. Application of neural network to 1-hour real data in Seoul metropolitan area and the Soyang River basin shows slightly good predictions. Therefore, when good data is available, the neural network is expected to predict the complicated rainfall successfully.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.6
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• pp.433-442
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• 2013

A set of bilingual terms is one of the most important factors in building language-related applications such as a machine translation system and a cross-lingual information system. In this paper, we introduce a new approach that automatically extracts candidates of English-Korean bilingual terms by using a bilingual parallel corpus and a basic English-Korean lexicon. This approach can be useful even though the size of the parallel corpus is small. A sentence alignment is achieved first for the document-level parallel corpus. We can align words between a pair of aligned sentences by referencing a basic bilingual lexicon. For unaligned words between a pair of aligned sentences, several assumptions are applied in order to align bilingual term candidates of two languages. A location of a sentence, a relation between words, and linguistic information between two languages are examples of the assumptions. An experimental result shows approximately 71.7% accuracy for the English-Korean bilingual term candidates which are automatically extracted from 1,000 bilingual parallel corpus.