• ETRI Journal
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• v.20 no.4
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• pp.301-326
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• 1998

In this paper, we have modeled and evaluated a new parallel processing system called Scalable Parallel computer Architecture based on Xbar (SPAX) for commercial applications. SMP systems are widely used as servers for commercial applications; however, they have very limited scalability. SPAX cost-effectively overcomes the SMP limitation by providing both scalability and application portability. To investigate whether the new architecture satisfies the requirements of commercial applications, we have built a system model and a workload model. The results of the simulation study show that the I/O subsystem becomes the major bottleneck. We found that SPAX can still meet the I/O requirement of the OLTP workload as it supports flexible I/O subsystem. We also investigated what will be the next most important bottleneck in SPAX and how to remove it. We found that the newly developed system network called Xcent-Net will not be a bottleneck in the I/O data path. We also show the optimal configuration that is to be considered for system tuning.

• 한국전산유체공학회:학술대회논문집
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• 2011.05a
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• pp.373-378
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• 2011

As the number of deeply-underground subway station(DUSS) increases, the safety measures for DUSS have been requested. In this research, Shingumho station (The line # 5, Depth: 46m) has been selected as case-study for the analysis of smoke-spread speed with the different fire strength. Field test data measured for actual fan in DUSS was applied as a condition of a simulation. The whole station was covered in this analysis and total of 4 million grids were generated for this simulation. The fire driven flow was analyzed case by case to compare the smoke-spread effect according to the fire strength. in order to enhance the efficiency of calculation, parallel processing by MPI was employed and large eddy simulation method in FDS code was adopted.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.27 no.4
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• pp.499-506
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• 2003

The design cycle associated with large engineering systems requires an initial decomposition of the complex system into design processes which are coupled through the transference of output data. Some of these design processes may be grouped into iterative subcycles. In analyzing or optimizing such a coupled system, it is essential to determine the best order of the processes within these subcycles to reduce design cycle time and cost. This is accomplished by decomposing large multidisciplinary problems into several sub design structure matrices (DSMs) and processing them in parallel This paper proposes a new method for parallel decomposition of multidisciplinary problems to improve design efficiency by using the multi-objective genetic algorithm and two sample test cases are presented to show the effect of the suggested decomposition method.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.12
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• pp.69-77
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• 2009

In this study an ANFIS-based trajectory tracking motion control algorithm is proposed for autonomous garage and parallel parking of a model car. The ANFIS controller is trained off-line using data set which obtained by Mandani fuzzy inference system and thereby the processing time decreases almost in half. The controller with a steering delay compensator is tuned through simulations performed under MATLAB/Simulink environment. Experiments are carried out with the model car for garage and parallel parking. The experimental results show that the trajectory tracking performance is satisfactory under various initial and road conditions

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.9
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• pp.1162-1170
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• 1995

In this paper, we present a message transfer scheme for efficient message passing in the hierarchically structured multiprocessor computer SPAX(Scalable Parallel Architecture computer based on X-bar network). The message transfer scheme provides interface not only with operating system but also with end users. In order to transfer two types of control message and data message efficiently, it supports both of memory-mapped transfer and DMA-based transfer. Dual-port RAMs are used as message buffers, and control and status registers provide efficient programming interface. Interlaced parity scheme is adopted for error control. If any error is detected at receiving node, errored packet is resent by sender according to retry mechanism. In conjunction with retry mechanism, watchdog timers are used to protect infinite waiting and repeated retry. The proposed message transfer scheme can be applied to input/output nodes and communication connection nodes as well as processing nodes in the SPAX.

• IE interfaces
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• v.7 no.3
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• pp.171-180
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• 1994

Defined is a Multi-level Parallel Machine Flow-Shop (MPMFS) which reflects some real world manufacturing situations. Just-In-Time (JIT) philosophy is applied to the MPMFS scheduling in order to achieve lowering work-in-process inventory level as well as meeting due dates. A schedule generating simulator is developed. The latest start time of each operation is determined by a backward simulation followed by another forward simulation to analyze the schedule feasibility and actual inventory level. Reasonable schedules are available through adjusting some parameters for allowance factors such as set-up times of machines and other environmental changes. The SLAMSYSTEM under Window is employed for this processing with some input/output data handling processes devised under DOS.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.42-47
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• 2020

In OFDM-based very high-speed communication systems, FFT/IFFT processor should have several properties of low-area and low-power consumption as well as high throughput and low processing latency. Thus, radix-2k MDF (multipath delay feedback) architectures by adopting pipeline and parallel processing are suitable. In MDF architecture, the feedback memory which increases in proportion to the input signal word-length has a large area and power consumption. This paper presents a feedback memory size reduction method of radix-22 MDF IFFT processor for OFDM applications. The proposed method focuses on reducing the feedback memory size in the first two stages of MDF architectures since the first two stages occupy about 75% of the total feedback memory. In OFDM transmissions, IFFT input signals are composed of modulated data and pilot, null signals. In order to reduce the IFFT input word-length, the integer mapping which generates mapped data composed of two signed integer corresponding to modulated data and pilot/null signals is proposed. By simulation, it is shown that the proposed method has achieved a feedback memory reduction up to 39% compared to conventional approach.

• MALSORI
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• no.52
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.