• ETRI Journal
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• v.31 no.6
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• pp.709-716
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• 2009

In this paper, we propose a novel reconfigurable processor using dynamically partitioned single-instruction multiple-data (DP-SIMD) which is able to process multimedia data. The SIMD processor and parallel SIMD (P-SIMD) processor, which is composed of a number of SIMD processors, are usually used these days. But these processors are inefficient because all processing units (PUs) should process the same operations all the time. Moreover, the PUs can process different operations only when every SIMD group operation is predefined. We propose a processor control method which can partition parallel processors into multiple SIMD-based processors dynamically to enhance efficiency. For performance evaluation of the proposed method, we carried out the inverse transform, inverse quantization, and motion compensation operations of H.264 using processors based on SIMD, P-SIMD, and DP-SIMD. Experimental results show that the DP-SIMD control method is more efficient than SIMD and P-SIMD control methods by about 15% and 14%, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.5
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• pp.36-42
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• 1980

In this study, multi-microprocessors system in which slave microprocessor is conrlected with master microprocessor bus through the DMA controller is designed by the use of four 8085 CPU. A high degree of processing efficiency could be obtained by making this system work parallel processing. The result of measuring relat ions bet ween working microproressor and system throughput was 70-80 percents lower than ideal value Master microprocessor takes charge of resource allocation and scheduling, common memory assigns communication between microprocessors and a store of common data. The met hod of detecting Pa rallelism from source Program composed by series is also suggested.

• The KIPS Transactions:PartB
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• v.13B no.3 s.106
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• pp.223-230
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• 2006

A window-based image processing is an elementary part of image processing area. Because window-based image processing is computationally intensive and data intensive, it is hard to perform ail of the operations of a window-based image processing in real-time by using a software program on general-purpose computers. This paper proposes a parallel hardware architecture that can perform a window-based image processing in real-time using FPGA(Field Programmable Gate Array). A dynamic threshold circuit and a local histogram equalization circuit of the proposed architecture are designed using VHDL(VHSIC Hardware Description Language) and implemented with an FPGA. The performances of both implementations are measured.

• Journal of Digital Convergence
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• v.12 no.11
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• pp.379-386
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• 2014

In this paper, the processing speed of Grabcut algorithm in order to efficiently improve the GPU (Graphics Processing Unit) for processing the data from the method. Grabcut algorithm has excellent performance object detection algorithm. Grabcut existing algorithms to split the foreground area and the background area, and then background and foreground K-cluster is assigned a cluster. And assigned to gradually improve the results, until the process is repeated. But Drawback of Grabcut algorithm is the time consumption caused by the repetition of clustering. Thus GPGPU (General-Purpose computing on Graphics Processing Unit) using the repeated operations in parallel by processing Grabcut algorithm to effectively improve the processing speed of the method. We proposed method of execution time of the algorithm reduced the average of about 95.58%.

• Smart Media Journal
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• v.2 no.3
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• pp.47-53
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• 2013

Recently convergence of IT in logistics system as a typical application RFID/NFC technology is being used, such as, according to the distribution of the flow is generated by a lot of big data. The Hadoop distributed system to collect data items produced by the parallel processing capabilities of logistics information and logistics information for the record management can create. Hadoop system to support the design and development of prototypes were approaching the possibility of its utilization.

• Annual Conference of KIPS
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• 2015.10a
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• pp.1102-1105
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• 2015

인터넷 발전이 가속화되고 SNS가 보급된 이후 과거와는 비교할 수 없을 정도로 큰 데이터 트래픽이 발생하고 있다. 기존의 DBMS는 이를 효과적으로 처리할 수 없었기 때문에 Hadoop과 같은 NoSQL이 탄생하였고, 최근 NoSQL 및 기존 SQL DBMS의 협업을 통해 유연하고 강력한 데이터 관리를 수행하는 연구가 진행되었다. 효율적인 질의 처리를 위한 대표적인 연구로 SQL 기반 분산 병렬 질의 처리 기법과 Hive등이 존재한다. 그러나 기존의 기법은 분산 병렬 환경을 고려하지 않아 SQL DBMS의 질의 결과를 효율적으로 Hive에 전송하지 못한다. 본 논문에서는 SQL DBMS에서 Hive로의 효율적인 SQL 데이터 이동을 위해 네트워크 비용을 최소화하는 기법을 제안하고, 제안하는 기법의 우수성을 제시한다.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• Journal of Digital Contents Society
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• v.14 no.3
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• pp.313-321
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• 2013

In recent, proliferation of mobile smart devices have led to big-data era, the importance of location-based services is increasing due to the exponential growth of trajectory related data. In order to process trajectory data, parallel processing platforms such as cloud computing and MapReduce are necessary. Currently, the researches based on MapReduce are on progress, but due to the MapReduce's properties in using batch processing and simple key-value structure, applying MapReduce framework for real time LBS is difficult. Therefore, in this research we propose a suitable system design on efficient indexing and search techniques for real time service based on detailed analysis on the properties of MapReduce.

• Journal of KIISE
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• v.42 no.4
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• pp.522-529
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• 2015

Ever since the R-tree was proposed to index multi-dimensional data, many efforts have been made to improve its query performances. One common trend to improve query performance is to parallelize query processing with the use of multi-core architectures. To this end, a GPU-base R-tree has been recently proposed. However, even though a GPU-based R-tree can exhibit an improvement in query performance, it is limited in its ability to handle large volumes of data because GPUs have limited physical memory. To address this problem, we propose MGR-tree (Multi-GPU R-tree), which can manage large volumes of data by dividing nodes into multiple GPUs. Our experiments show that MGR-tree is up to 9.1 times faster than a sequential search on a GPU and up to 1.6 times faster than a conventional GPU-based R-tree.