• Title/Summary/Keyword: Parallel connecting

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Application of SFCL on Bus Tie for Parallel Operation of Power Main Transformers in a Fuel Cell Power Systems

  • Chai, Hui-Seok;Kang, Byoung-Wook;Kim, Jin-Seok;Kim, Jae-Chul
    • Journal of Electrical Engineering and Technology
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    • v.10 no.6
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    • pp.2256-2261
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    • 2015
  • In the power plant using high temperature fuel cells such as Molten Carbonate Fuel Cell(MCFC), and Solid Oxide Fuel Cell(SOFC), the generated electric power per area of power generation facilities is much higher than any other renewable energy sources. - High temperature fuel cell systems are capable of operating at MW rated power output. - It also has a feature that is short for length of the line for connecting the interior of the generation facilities. In normal condition, these points are advantages for voltage drops or power losses. However, in abnormal condition such as fault occurrence in electrical system, the fault currents are increased, because of the small impedance of the short length of power cable. Commonly, to minimize the thermal-mechanical stresses on the stack and increase the systems reliability, we divided the power plant configuration to several banks for parallel operation. However, when a fault occurs in the parallel operation system of power main transformer, the fault currents might exceed the interruption capacity of protective devices. In fact, although the internal voltage level of the fuel cell power plant is the voltage level of distribution systems, we should install the circuit breakers for transmission systems due to fault current. To resolve these problems, the SFCL has been studied as one of the noticeable devices. Therefore, we analyzed the effect of application of the SFCL on bus tie in a fuel cell power plants system using PSCAD/EMTDC.

Crown angulations of posterior teeth of normal occlusion measured from marginal ridge plane (변연융선평면을 계측기준으로 한 정상교합자의 구치부 치관경사도에 관한 연구)

  • Lim, Sung-Hoon;Yoon, Young-Jooh;Kim, Kwang-Won
    • The korean journal of orthodontics
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    • v.28 no.5 s.70
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    • pp.731-740
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    • 1998
  • In the previous studies about prescription of preadjusted appliance, occlusal plane was used as a reference plane for crwon angulation (tip) measurement. But this reference plane is not parallel to the line connecting the facial axis points at which the centers of brackets are positioned (Andrews' plane), due to the curve of Spee. Therefore, we developed a new reference plane unaffected by the curve of Sun and more parallel to the Andrews' plane. It is an imaginary line connecting mesial and distal marginal ridges of each posterior tooth, and we named it 'marginal ridge plane'. In this study, crown angulations of posterior teeth of 29 normal occlusion samples were measured and measurements from both reference planes were compared. Crown angulation measurements measured from occlusal plane were different from crown angulation measurements from marginal ridge plane in the upper and lower 2nd molars (p<0.01), md 1st premolars (p<0.05). These results were analyzed as the crown angulation measurements from occlusal plane were affected by the curve of Spee. Crown angulations should be varied according to the amount of curve of Spee to maintain the continuity of marginal ridges. To solve this problem, determining bracket angulation as the bracket slot is parallel to the marginal ridge plane of each posterior teeth is recommended.

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Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system

  • Igarashi, Akira
    • Smart Structures and Systems
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    • v.14 no.6
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    • pp.1131-1150
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    • 2014
  • One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

Compact Multi-harmonic Suppression LTCC Bandpass Filter Using Parallel Short-Ended Coupled-Line Structure

  • Wang, Xu-Guang;Yun, Young;Kang, In-Ho
    • ETRI Journal
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    • v.31 no.3
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    • pp.254-262
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    • 2009
  • This paper presents a novel simple filter design method based on a parallel short-ended coupled-line structure with capacitive loading for size reduction and ultra-broad rejection of spurious passbands. In addition, the introduction of a cross-coupling capacitor into the miniaturized coupled-line can create a transmission zero at the second harmonic frequency for better frequency selectivity and attenuation level. The aperture compensation technique is also applied to achieve a strong coupling in the coupled-line section. The influence of using the connecting transmission line to cascade two identical one-stage filters is studied for the first time. Specifically, such a two-stage bandpass filter operating at 2.3 GHz with a fractional bandwidth of 10% was designed and realized with low-temperature co-fired ceramic technology for application in base stations that need high power handling capability. It achieved attenuation in excess of -40 dB up to $4f_0$ and low insertion loss of -1.2 dB with the size of 10 mm ${\times}$ 7 mm ${\times}$ 2.2 mm. The measured and simulated results showed good agreement.

A Readout IC Design for the FPN Reduction of the Bolometer in an IR Image Sensor

  • Shin, Ho-Hyun;Hwang, Sang-Joon;Jung, Eun-Sik;Yu, Seung-Woo;Sung, Man-Young
    • Transactions on Electrical and Electronic Materials
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    • v.8 no.5
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    • pp.196-200
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    • 2007
  • In this paper, we propose and discuss the design using a simple method that reduces the fixed pattern noise(FPN) generated on the amorphous Si($\alpha-Si$) bolometer. This method is applicable to an IR image sensor. This method can also minimize the size of the reference resistor in the readout integrated circuit(ROIC) which processes the signal of an IR image sensor. By connecting four bolometer cells in parallel and averaging the resistances of the bolometer cells, the fixed pattern noise generated in the bolometer cell due to process variations is remarkably reduced. Moreover an $\alpha-Si$ bolometer cell, which is made by a MEMS process, has a large resistance value to guarantee an accurate resistance value. This makes the reference resistor be large. In the proposed cell structure, because the bolometer cells connected in parallel have a quarter of the original bolometer's resistance, a reference resistor, which is made by poly-Si in a CMOS process chip, is implemented to be the size of a quarter. We designed a ROIC with the proposed cell structure and implemented the circuit using a 0.35 um CMOS process.

A Basic Study of Thermal-Fluid Flow Analysis Using Grid Computing (그리드 컴퓨팅을 이용한 열유동 해석 기법에 관한 기초 연구)

  • Hong, Seung-Do;Ha, Yeong-Man;Cho, Kum-Won
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.28 no.5
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    • pp.604-611
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    • 2004
  • Simulation of three-dimensional turbulent flow with LES and DNS lakes much time and expense with currently available computing resources and requires big computing resources especially for high Reynolds number. The emerging alternative to provide the required computing power and working environment is the Grid computing technology. We developed the CFD code which carries out the parallel computing under the Grid environment. We constructed the Grid environment by connecting different PC-cluster systems located at two different institutes of Pusan National University in Busan and KISTI in Daejeon. The specification of PC-cluster located at two different institutes is not uniform. We run our parallelized computer code under the Grid environment and compared its performance with that obtained using the homogeneous computing environment. When we run our code under the Grid environment, the communication time between different computer nodes takes much larger time than the real computation time. Thus the Grid computing requires the highly fast network speed.

Design of an Expandable VLSI Rebound Sorter (확장형 VLSI 리바운드 정렬기의 설계)

  • Yun, Ji-Heon;Ahn, Byoung-Chul
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.3
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    • pp.433-442
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    • 1995
  • This paper presents an improved VLSI implementation of a parallel sorter to achieve O(Ν) time complexity. Many fast VLSI sort algorithms have been proposed for sorting N elements in O(log Ν) time. However, most such algorithms proposed have complex network structure without considering data input and output time. They are also very difficult to expand or to use in real applications. After analyzing the chip area and time complexity of several parallel sort algorithms with overlapping data input and output time, the most effective algorithm, the rebound sort algorithm, is implemented in VLSI with some improvements. To achieve O(Ν) time complexity, an improved rebound sorter is able to sort 8 16-bits records on a chip. And it is possible to sort more than 8 records by connecting chips in a chain vertically.

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Analysis of Electromagnetic Wave Scattering Characteristics of Dielectric Barrier Discharge Plasma (유전체 장벽 방전 플라즈마의 전자파 산란 특성 분석)

  • Lee, Soo-Min;Oh, Il-Young;Hong, Yong-Jun;Yook, Jong-Gwan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.3
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    • pp.324-330
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    • 2013
  • This paper presented measurement results of scattering characteristics of dielectric barrier discharge (DBD) plasma at atmospheric pressure. In this paper, plasma actuator is fabricated by parallel connecting of basic configuration of DBD plasma actuator, then plasma could be generated by applying 14 kV, 4 kHz of high voltage generator. In order to measure the scattering characteristics of DBD plasma, in this paper, two horn antennas and vector network analyzer are used to compare the S-parameter. Because of the structure of fabricated plasma generator, different result is obtained as antenna polarization changes. When antenna polarization is parallel to electrodes of plasma generator, the scattered field is reduced by 2 dB in maximum. In addition, for parallel polarization case, PEC is set up behind the plasma generator to measure backward scattered field. When the observation angles are $40^{\circ}C$ and $60^{\circ}C$, the amount of reduced scattered field is 2 dB in maximum at 5 GHz.

The Bigdata Processing Environment Building for the Learning System (학습 시스템을 위한 빅데이터 처리 환경 구축)

  • Kim, Young-Geun;Kim, Seung-Hyun;Jo, Min-Hui;Kim, Won-Jung
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.7
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    • pp.791-797
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    • 2014
  • In order to create an environment for Apache Hadoop for parallel distributed processing system of Bigdata, by connecting a plurality of computers, or to configure the node, using the configuration of the virtual nodes on a single computer it is necessary to build a cloud fading environment. However, be constructed in practice for education in these systems, there are many constraints in terms of cost and complex system configuration. Therefore, it is possible to be used as training for educational institutions and beginners in the field of Bigdata processing, development of learning systems and inexpensive practical is urgent. Based on the Raspberry Pi board, training and analysis of Big data processing, such as Hadoop and NoSQL is now the design and implementation of a learning system of parallel distributed processing of possible Bigdata in this study. It is expected that Bigdata parallel distributed processing system that has been implemented, and be a useful system for beginners who want to start a Bigdata and education.

Indoor Autonomous Driving through Parallel Reinforcement Learning of Virtual and Real Environments (가상 환경과 실제 환경의 병행 강화학습을 통한 실내 자율주행)

  • Jeong, Yuseok;Lee, Chang Woo
    • Journal of Korea Society of Industrial Information Systems
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    • v.26 no.4
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    • pp.11-18
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    • 2021
  • We propose a method that combines learning in a virtual environment and a real environment for indoor autonomous driving through reinforcement learning. In case of learning only in the real environment, it takes about 80 hours, but in case of learning in both the real and virtual environments, it takes 40 hours. There is an advantage in that it is possible to obtain optimized parameters through various experiments through fast learning while learning in a virtual environment and a real environment in parallel. After configuring a virtual environment using indoor hallway images, prior learning was carried out on the desktop, and learning in the real environment was conducted by connecting various sensors based on Jetson Xavier. In addition, in order to solve the accuracy problem according to the repeated texture of the indoor corridor environment, it was possible to determine the corridor wall object and increase the accuracy by learning the feature point detection that emphasizes the lower line of the corridor wall. As the learning progresses, the experimental vehicle drives based on the center of the corridor in an indoor corridor environment and moves through an average of 70 steering commands.