• The Transactions of the Korea Information Processing Society
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• v.6 no.10
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• pp.2816-2822
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• 1999

In this paper, a fast thinning method for fingerprint image by separating end and bifurcation region is proposed. To detect feature points in automatic fingerprint identification system, thinning of fingerprint is essential. The end and bifurcation regions in ridge line are separated by means of run-length coding, and parallel thinning method is applied to the separated regions. The rest parts except the end and bifurcation regions are processed by connecting center points of each run. The performance of the proposed method has been evaluated by CPU processing time and thinness measurement. By the experimental results, the proposed method is fast and has high thinness value.

• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.3
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• pp.106-111
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the parallel operations and SAD unit control using pattern information, the proposed IME instruction supports not only full search algorithm but also other fast search algorithms. The hardware size is 77K gates for each Processing Element Group (PEG) which has 256 SAD PEs. The proposed ASIP runs at 160MHz with sixteen PEGs and it can handle 1080p@30 frame in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.8
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• pp.1613-1621
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• 2015

This paper analyzes the rate adaptation scheme and suggests applicable strategy of the MCS(Modulation and Coding Scheme) for improving DCF throughput in the IEEE 802.11ad and 802.11ad wireless LAN. IEEE 802.11ac and 802.11ad wireless LAN provide MCS technique that dynamically adjusts modulation level and code rate to the time-varying channel conditions in order to obtain considerably high data rates. But these standards did not provide rate adaptation algorithm, so this paper surveyes rate adaptation algorithm and suggests MCS scheme applied to IEEE 802.11ac and 802.11ad wireless LAN. Specially A MAC(Medium Access Control) layer throughput is evaluated over error-prone channel in the IEEE 802.11ac-based wireless LAN. In this evaluation, DCF (Distributed Coordination Function) protocol and A-MPDU (MAC Protocol Data Unit Aggregation) scheme are used. Using theoretical analysis method, the MAC saturation throughput is evaluated with the PER (Packet Error Rate) on the condition that the number of station, transmission probability, the number of parallel beams and the number of frames in each A-MPDU are variables.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.2
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• pp.62-67
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• 2001

In the recent mobile communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that need a large time delay over the reception process. Moreover, Turbo Code has been known as the robust ending method with the confidence over the fading channel. The International Telecommunication Union(ITU) has recently adopted as the standardization of the channel coding over the third generation mobile communications such as IMT-2000. Therefore, in this paper, we proposed of the method to improve the conventional performance with the parallel concatenated 4-New Turbo Decoder using MAP a1gorithm in spite of complexity increasement. In the real-time video and video service over the third generation mobile communications, the performance of the proposed method was analyzed by the reduced decoding delay using the variable decoding method by computer simulation over AWGN and fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Molecules and Cells
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• v.19 no.1
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• pp.104-113
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• 2005

Large inversions are well characterized in the chloroplast genomes of land plants. In contrast, reports of small inversions are rare and involve limited plant groups. In this study, we report the widespread occurrence of small inversions ranging from 5 to 50 bp in fully and partially sequenced chloroplast genomes of both monocots and dicots. We found that small inversions were much more common than large inversions. The small inversions were scattered over the chloroplast genome including the IR, SSC, and LSC regions. Several small inversions were uncovered in chloroplast genomes even though they shared the same overall gene order. The majority of these small inversions were located within 100 bp downstream of the 3' ends of genes. All had inverted repeat sequences, ranging from 11 to 24 bp, at their ends. Such small inversions form stem-loop hairpin structures that usually have the function of stabilizing the corresponding mRNA molecules. Intra-molecular recombination between the inverted sequences in the stem-forming regions are responsible for generating flip-flop orientations of the loops. The presence of two different orientations of the stem-loop in the trnL-F noncoding region of a single species of Jasminum elegans suggests that a short inversion can be generated within a short period of time. Small inversions of non-coding sequences may influence sequence alignment and character interpretation in phylogeny reconstructions, as shown in nine species of Jasminum. Many small inversions may have been generated by parallel or back mutation events during chloroplast genome evolution. Our data indicate that caution is needed when using chloroplast non-coding sequences for phylogenetic analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.