• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.28-34
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• 2015

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.36-42
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• 2010

This paper presents a hybrid approach to the construction of quasi-cyclic (QC) low-density parity-check (LDPC) codes based on parallel bundles in Euclidean geometries and circulant permutation matrices. Codes constructed by this method are shown to be regular with large girth and low density. Simulation results show that these codes perform very well with iterative decoding and achieve reasonably large coding gains over uncoded system.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.409-410
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• 2013

동영상 압축 기술 HEVC(High Efficiency Video Coding)는 ITU-T(VCEG)와 ISO-IEC(MPEG)에서 JCT-VC라는 팀을 이루어 공동으로 표준화를 완성 단계에 이르렀다. 기존 표준보다 약 50%의 성능 향상을 가져왔지만 다양한 최신 압축 기술을 사용함에 따라 부호화 및 보호화의 복잡도가 매우 복잡한 단점을 가진다. 제안하는 방법은 슬라이스 단위의 프로세싱을 OpenMP를 통한 병렬 구조를 적용하는 방법과 GPU 가속 모델을 적용한 방법을 통해 고화질 영상의 실시간 부호화 및 복호화에 대해 분석한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.683-686
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• 2000

A new approach to the task of aligning a robot using camera is presented in this paper. We apply an elitist GA to find the joints angles of manipulator to reach target position instead of using nonlinear least error method. Since it employs parallel search and have good performance in solving optimization problems. In order to improve convergence speed, the floating coding method and geometry constraint conditions are used. Experiments are carried out to exhibit the effectiveness of vision-based control using elitist genetic algorithm.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2271-2272
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• 2008

Recently, LDPC codes received a lot of attention in 4G. LDPC codes perform good error correction at high SNR. But LDPC codes are complex design and not good at low SNR. At low SNR, convolution codes and turbo codes show more good performance than LDPC codes. The main subject presented in this study is that parallel encoding and decoding according to SNR. The system chooses convolution codes at low SNR and chooses LDPC codes at high SNR.

• Journal of electromagnetic engineering and science
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• v.4 no.1
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• pp.17-22
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• 2004

In this paper, we implement an efficient MLC/PDL system for AWGN channels. In terms of the tradeoff between the hardware implementation and system performance, proposed algebra LDPC codes are optimized by the Gaussian approximation(GA) according to the rate of each level assigned by the capacity rule and chosen as the component code. System performance with Ungerboeck Partitioning(UP), Miked Partitioning(MP) and Gray Mapping(GM) of 8PSK are evaluated, respectively. Many results are presented in this paper; they can indicate that the proposed MLC/PDL system using optimized algebra LDPC codes with different code rate, capacity rule and Gray mapping(GM) can achieve the best performance.

• Journal of Genetic Medicine
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• v.12 no.1
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• pp.6-11
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• 2015

Intellectual disability (ID) is the most common disability among people under the age of 20 years. In the absence of obvious non-genetic causes of ID, the majority of cases of severe ID are thought to have a genetic cause. The advent of technologies such as array comparative genomic hybridization, single nucleotide polymorphism genotyping arrays, and massively parallel sequencing has shown that de novo copy number variations and single nucleotide variations affecting coding regions are major causes of severe ID. This article reviews the genetic causes of ID along with diagnostic approaches for this disability.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.12
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• pp.27-34
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• 1994

Block matching motion estimation is the most widely used method for motion compensated coding of image sequences. Based on a two dimensional systolic array, VLSI architecture and implementation of the full search block matching algorithm are described in this paper. The proposed architecture improves conventional array architecture by designing efficient processing elements that can control the data prodeuced by efficient search window division method. The advantages are that 1) it allows serial input to reduce pin counts for efficient composition of local memories but performs parallel processing. 2) It is flexible and can adjust to dimensional changes of search windows with simple control logic. 3) It has no idel time during the operation. 4) It can operate in real/time for low and main level in MPEG-2 standard. 5) It has modular and regular structure and thus is sutiable for VLSI implementation.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.66-69
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• 2000

In this paper, we propose a progressive transmission of a video using a 2$\times$2$\times$2 DCT First of all, the video data is transformed into multiresolution represented video data using a 2$\times$2$\times$2 DCT. Then. it is represented by a 3-D EZT(Embedded Zero Tree) coding fur the progressive transmission with a bit-rate scalability. The proposed progressive transmission algorithm needs much less computations and buffer memories than the higher-order convolution based wavelet filter. Also, since the 2$\times$2$\times$2 DCT requires independent local computations, parallel processing can be applied.