• Title/Summary/Keyword: Parallel array structure

Search Result 89, Processing Time 0.027 seconds

A LSI/VLSI Logic Design Structure for Testability and its Application to Programmable Logic Array Design (Test 용역성을 고려한 LSI/VLSI 논리설계방식과 Programmable Logic Array에의 응용)

  • Han, Seok-Bung;Jo, Sang-Bok;Im, In-Chil
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.21 no.3
    • /
    • pp.26-33
    • /
    • 1984
  • This paper proposes a new LSI/VLSI logic design structure which improves shift register latches in conventional LSSD. Test patterns are easily generated and fault coverage is enhanced by using the design structure. The new parallel shift register latch can be applied to the design of easily testable PLA's. In this case, the number of test patterns is decreased and decoders which are added to the feedback inputs in conventional PLA's using LSSD are not necessary.

  • PDF

A VLSI array implementation of vector-radix 2-D fast DCT (Vector-radix 2차원 고속 DCT의 VLSI 어레이 구현)

  • 강용섬;전흥우;신경욱
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.32A no.1
    • /
    • pp.234-243
    • /
    • 1995
  • An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

  • PDF

Fabrication of the Optical Fiber-Photodiode Array Module Using Si v-groove (실리콘 v-groove를 이용한 광섬유-광검출기 어레이 모듈 제작)

  • 정종민;지윤규;박찬용;유지범;박경현;김홍만
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.31A no.6
    • /
    • pp.88-97
    • /
    • 1994
  • We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.

  • PDF

Design of a systolic array for forward-backward propagation of back-propagation algorithm (역전파 알고리즘의 전방향, 역방향 동시 수행을 위한 스스톨릭 배열의 설계)

  • 장명숙;유기영
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.33B no.9
    • /
    • pp.49-61
    • /
    • 1996
  • Back-propagation(BP) algorithm needs a lot of time to train the artificial neural network (ANN) to get high accuracy level in classification tasks. So there have been extensive researches to process back-propagation algorithm on parallel processors. This paper prsents a linear systolic array which calculates forward-backward propagation of BP algorithm at the same time using effective space-time transformation and PE structure. First, we analyze data flow of forwared and backward propagations and then, represent the BP algorithm into data dapendency graph (DG) which shows parallelism inherent in the BP algorithm. Next, apply space-time transformation on the DG of ANN is turn with orthogonal direction projection. By doing so, we can get a snakelike systolic array. Also we calculate the interval of input for parallel processing, calculate the indices to make the right datas be used at the right PE when forward and bvackward propagations are processed in the same PE. And then verify the correctness of output when forward and backward propagations are executed at the same time. By doing so, the proposed system maximizes parallelism of BP algorithm, minimizes th enumber of PEs. And it reduces the execution time by 2 times through making idle PEs participate in forward-backward propagation at the same time.

  • PDF

A Slot Away Antenna with a Simple Feed Structure for Broadband Multimedia Wireless Applications (단순한 급전 구조를 갖는 Broadband Multimedia Wireless System(BMWS)용 슬롯 배열 안테나)

  • 성영제;이정수;오순수;문종용;최원규;표철식;최재익;김영식
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.14 no.3
    • /
    • pp.209-216
    • /
    • 2003
  • We design and fabricate slot array antenna for BMWS(Broadband Multimedia Wireless System) applications. This paper presents a simple feed structure, which consists of two horns and a parallel-plate waveguide, because antennas operating at 40.5 GHz~43.5 GHz have considerable feeding losses. The simple feed structure has the advantages of high-efficiency and mass-production. The fabricated antenna has a gain of 25.8 dBi with a sidelobe level below -18 ㏈ and a 3 ㏈ beamwidth of approximately 3$^{\circ}$ in the E-plane. In case of H-plane, a 3 ㏈ beamwidth is 17$^{\circ}$ and a sidelobe level is suppressed to below -27 ㏈. The experimental results are in good agreement with the simulation results. The authors expect that narrow 3 ㏈ beamwidth is obtained by combining a few proposed slot array antennas in parallel.

Structure of a single polymer chain confined in a dense array of nanoposts

  • Joo, Heesun;Kim, Jun soo
    • Proceeding of EDISON Challenge
    • /
    • 2015.03a
    • /
    • pp.48-52
    • /
    • 2015
  • Control of polymer conformations in heterogeneous confinement plays an important role in natural and engineering processes. We present a simulation study on the conformational structure and dynamics of a single, flexible polymer in a dense array of nanoposts with different sizes and separations, especially, when the volume of the interstitial space formed between four nanoposts is less than the size of the polymer chain. When a polymer is placed in the array of nanoposts, the size of polymer increases compared with that in the absence of nanoposts due to the confinement effect. It is shown that when a polymer is confined in the array of nanoposts the chain is elongated in the direction parallel to the nanoposts. As the interstitial volume between four nanoposts decreases either by increasing the nanopost diameter or by decreasing the separation between nanoposts, the chain elongation becomes more pronounced. On the contrary, the polymer size varies in a non-monotonic fashion, with an initial elongation followed by a chain contraction, as the interstitial volume is reduced both by increasing the nanopost diameter and decreasing the separation at the same time while keeping constant the width of the passageway between two nanoposts. The simulation analysis shows that the non-monotonic dependence of polymer size is determined by interplay between the chain alignment along the nanoposts in each interstitial volume and the chain spreading through passageways over several interstitial volume.

  • PDF

Wind loads on solar panels mounted parallel to pitched roofs, and acting on the underlying roof

  • Leitch, C.J.;Ginger, J.D.;Holmes, J.D.
    • Wind and Structures
    • /
    • v.22 no.3
    • /
    • pp.307-328
    • /
    • 2016
  • This paper describes an investigation of the net wind loads on solar panels and wind loads on the underlying roof surface for panels mounted parallel to pitched roofs of domestic buildings. Typical solar panel array configurations were studied in a wind tunnel and the aerodynamic shape factors on the panels were put in a form appropriate for the Australian/New Zealand Wind Actions Standard AS/NZS 1170.2:2011. The results can also be used to obtain more refined design data on individual panels within an array. They also suggest values for the aerodynamic shape factors on the roof surface under the panels, based on a gust wind speed at roof height, of ${\pm}0.5$ for wind blowing parallel to the ridge, and ${\pm}0.6$ for wind blowing perpendicular to the ridge. The net loads on solar arrays in the middle portion of the roof are larger than those on the same portion of the roof without any solar panels, thus resulting in increased loads on the underlying roof structure.

Performance of the Viterbi Decoder using Analog Parallel Processing circuit with Reference position (아날로그 병렬 처리 망을 이용한 비터비 디코더의 기준 입력 인가위치에 따른 성능 평가)

  • Kim, Hyung-Jung;Kim, In-Cheol;Lee, Wnag-Hee;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
    • /
    • 2006.10c
    • /
    • pp.378-380
    • /
    • 2006
  • A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

  • PDF

Fabrication of Beta-phase Poly(9,9-dioctylfluorene) Nanowire Arrays for Polymer Light-Emitting Diode Using Direct Printing Method

  • Baek, Jang-Mi;Lee, Gi-Seok;Seong, Myeong-Mo
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2012.02a
    • /
    • pp.560-560
    • /
    • 2012
  • We report a one-step fabrication method of Poly(9,9-dioctylfluorene) (PFO) nanowire array with pronounced ${\beta}$-Phase. We use liquid-bridge-mediated nanotransfer molding (LB-nTM) which is a new direct nano-patterning method based on the direct transfer of various materials from a mold to a substrate via liquid layer. The formation of the ${\beta}$-phase morphology in the resulting PFO nanowire array was evidenced by the presence of an absorption peak at 435nm. With the collection polarizer oriented parallel to the wire long axis, the PL emission was most intense and an emission dichroic ratio, DRE, of 3.7 was determined. The nanowire array have been investigated by scanning electron microscopy (SEM). Also, we simply fabricated structure of device of ITO/PFO nanowire arrays/Al and the electroluminescence spectra were recorded at various applied voltage.

  • PDF

Angle-Range-Polarization Estimation for Polarization Sensitive Bistatic FDA-MIMO Radar via PARAFAC Algorithm

  • Wang, Qingzhu;Yu, Dan;Zhu, Yihai
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.14 no.7
    • /
    • pp.2879-2890
    • /
    • 2020
  • In this paper, we study the estimation of angle, range and polarization parameters of a bistatic polarization sensitive frequency diverse array multiple-input multiple-output (PSFDA-MIMO) radar system. The application of polarization sensitive array in receiver is explored. A signal model of bistatic PSFDA-MIMO radar system is established. In order to utilize the multi-dimensional structure of array signals, the matched filtering radar data can be represented by a third-order tensor model. A joint estimation of the direction-of-departure (DOD), direction-of-arrival (DOA), range and polarization parameters based on parallel factor (PARAFAC) algorithm is proposed. The proposed algorithm does not need to search spectral peaks and singular value decomposition, and can obtain automatic pairing estimation. The method was compared with the existing methods, and the results show that the performance of the method is better. Therefore, the accuracy of the parameter estimation is further improved.