• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.236-242
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• 2004

In this paper, we propose an approach to parallelize a load balancing algorithm that was shown to be very effective in distributing workload for parallel computations. Load balancing algorithms are required in executing parallel program efficiently As a parallel computation model, we used dynamically growing tree structure that can be found in many application problems. The load balancing algorithm tries to balance the workload among processors while keeping the communication cost under certain limit. We show how the load balancing algorithm is effectively parallelized on mesh and hypercube interconnection networks, and analyzed the time complexity for each case to show that parallel algorithm actually reduced the various overhead.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.81-90
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• 2000

Parallel manipulator is suitable for the high precise task because it than has higher stiffness, larger load capacity and more excellent precision, due to the closed-lop structure, than serial manipulator. But the controller design for parallel manipulator is difficult because the parallel manipulator has both the complexity of structure and the interference of actuators. The precision improvement of parallel manipulator using a classical linear control scheme is difficult because the parallel manipulator has the tough nonlinear characteristics. In this paper, firstly, the kinematic analysis of a parallel manipulator used at the experiments is performed so as to show the controllability. The analysis of internal singular configuration of the workspace is performed using the kinematic isotropic index so a sto show the limitation of control performance of a simple linear controller with fixed control gains. Secondly, a control scheme is designed by using an adaptive fuzzy logic controller so that active joints of the parallel manipulator track more precisely the desired input trajectory. This adaptive fuzzy logic controller so that active joints of the parallel manipulator track more precisely the desired input trajectory. This adaptive fuzzy logic controller is often used for the control of nonlinear system because it has both the inference ability and the learning ability. Lastly, the effeciency of designed control scheme is demonstrated by the real-time control experiments with IBM PC interface logic H/W and S/W of my won making. The experimental results was a success.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1166-1169
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• 1987

A new analog-la-digital structure. called cyclic-parallel analog-to-digital(A/D) converter, has been developed for video applications. It consists of a M-bit parallel A/D converter, a digital-to-analog(D/A) converter, a differencing amplifier with gain of $2^M$ and two sample-and-hold circuits. In this structure, the input signal is circulated around the circuits K times, thereby converted into a MK-bit digital word. The proposed converter retains speed advantages of conventional series-parallel converters, with half reduced circuit components.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.88-96
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• 1996

Periodically slotted dielectricalloy filled parallel-plate waveguide as a leaky wave antenna is designed and fabricated at the center frequency of 10.0GHz. The antenna was fed by use of a hog-horn structure. The hog-horn and the two side walls and the lower plate of parallel-plate waveguide were fabricated form duralumin. The upper plate of parallel-plate waveguide with 48 periodic slots was made of copper plate of 1mm thickness. The dielectric material inside the parallel-plate waveguide was chosen to be paraffin. The experimental radiation pattern for the fbricated antenna was compared with the theoretical results for the finite periodic structure.

• Proceedings of the KSME Conference
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• 2000.11a
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• pp.818-823
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• 2000

In practical design studies, most of designers solve multidisciplinary problems with complex design structure. These multidisciplinary problems have hundreds of analysis and thousands of variables. The sequence of process to solve these problems affects the speed of total design cycle. Thus it is very important for designer to reorder original design processes to minimize total cost and time. This is accomplished by decomposing large multidisciplinary problem into several multidisciplinary analysis subsystem (MDASS) and processing it in parallel. This paper proposes new strategy for parallel decomposition of multidisciplinary problem to raise design efficiency by using genetic algorithm and shows the relationship between decomposition and multidisciplinary design optimization (MDO) methodology.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.6
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• pp.294-300
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• 1999

There is a growing interest in hybrid electric vehicles due to environmental concerns. Recent efforts are directed toward developing an improved main component systems for the hybrid electric vehicle applications. Soon after the introduction of electric starter for internal combustion engine early this century, despite being energy efficient and nonpolluting, electric vehicle lost the battle completly to internal combustion engine due to its limited range and inferior performance. Hybrid Electric vehicles offer the most promising solutions to reduce the emission of vehicles. This paper describes a method for cost reduction estimation of parallel hybrid electric vehicle. We used a cost reduction structure that consisted of five major subsystems (three-type and two-type motor) for parallel hybrid electric vehicle. Especially, we estimated the potential for cost reductions in parallel hybrid electric vehicle as a function of time using the learning curve. Also, we estimated the potentials of cost by depreciation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.189-196
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• 1994

This paper describes a parallel computing algorithm in Gauss elimination of Jacobian matrix to large-scale power system. The structure of Jacobian matrix becomes different according to ordering method of buses. In sequential computation buses are ordered to minimize the number of fill-in in the triangulation of the Jacobian matrix. The proposed method develops the parallelism in the Gauss elimination by using ND(nested dissection) ordering. In this procedure the level structure of the power system network is transformed to be long and narrow by using end buses which results in balance of computing load among processes and maximization of parallel computation. Each processor uses the sequential computation method to preserve the sqarsity of matrix.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.10a
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• pp.307-314
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• 2000

A parallel condensation algorithm for efficient dynamic analysis of three-dimensional large-scale structures is presented. The algorithm is developed for a user-friendly and cost effective high-performance computing system on a collection of Pentium processors connected via a 100 Mb/s Ethernet LAN. To harness the parallelism in the computing system effectively, a large-scale structure is partitioned into a number of substructures equal to the number of computers in the computing system Then, for reduction in the size of an eigenvalue problem the computations required for static condensation of each substructure is processed concurrently on each slave computer. The performance of th proposed parallel algorithm is demonstrated by applying to dynamic analysis of a three dimensional structure. The results show that how the parallel algorithm facilitates the efficient use of a small number of low-cost personal computers for dynamic analysis of large-scale structures.