• 한국정보처리학회논문지
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• 제7권9호
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• pp.2827-2835
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• 2000

최근, 멀티미디어 정보처리와 같은 대규모 데이터 처리에 필수적인 입출력 시스템의 성능을 높이기 위하여 많은 관심이 집중되고 있으며, 고성능 병렬화일 시스템에 관한 연구도 이런 노력에 속한다. 본 연구에서는 고성능 병렬화일 시스템을 위한 효율적인 디스크 할당 방법을 제안한다. 즉, 병렬화일의 자료 분산(data declustering)특성을 이용하여 병렬화일에 대한 병렬도 개념을 정의하고, 이를 기반으로 여러 병렬화일들이 동시에 처리되는 경우에, 최대의 작업처리량(throughput)을 얻기 위한 각 병렬화일에 적합한 디스크상의 자료 분산 정도를 계산하는 방법을 제안한다. 또한 동시에 처리되는 병렬화일들이 많이 늘어날수록, 최대의 작업처리량을 얻기 위한 계산이 너무 복잡해지므로, 효율적인 근사 디스크 할당 알고리즘도 아울러 제안한다. 제안된 근사 알고리즘은 계산이 간단하고, 특히 입출력 작업부하(workload)가 높은 환경에서는 매우 효율적임을 보여준다. 또한 입출력 요구들의 도착 비율이 무한대일 경우, 근사 알고리즘만을 이용하여도 최대 작업처리량을 위한 최적 디스크 할당을 얻을 수 있음을 증명하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.274-276
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• 2007

In this paper, a low cost and high reliability control scheme is proposed for 400Hz UPS system operated in parallel. The proposed control scheme is consisted of two parts which are synchronization and load sharing control. The synchronization control is achieved by discrete logic ICs and analog circuit. The load sharing control is realized by current transformers (CTs) without any controller. Therefore, This proposed control scheme is rather simple and the cost may be decreased, compared with control scheme using expensive controller such as DSP and CAN. The practical feasibility of the proposed control scheme is proved by analysis and simulation.

• 전기학회논문지
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• 제64권5호
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• pp.708-717
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• 2015

This paper proposes a new reduction scheme of circulating current when two units of BESS (Battery Energy Storage System) are operated in parallel with conventional droop control. In case of using conventional droop, the terminal voltage of each BESS are not equal due to the unequal line impedance, which causes the circulating current. The operation performance of BESS is critically dependant on the circulating current because it increases system losses which causes the increasement of required system rating. This paper introduces a new reduction scheme of circulating current in which the terminal voltage difference of each BESS is compensated by adding feed-forward path of line voltage drop to the droop control. The feasibility of proposed scheme was first verified by computer simulations with PSCAD/EMTDC software. After then a hardware prototype with 5kW rating was built in the lab and many experiments were carried out. The experimental results were compared with the simulation results to confirm the feasibility of proposed scheme. Two parallel operating BESS with proposed scheme shows more accurate performance to suppress the circulating current than those with the conventional droop control.

• 한국멀티미디어학회논문지
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• 제22권2호
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• pp.231-241
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• 2019

Bulk-loading an R-tree can be a good approach to build an efficient one. However, it takes a lot of time to bulk-load an R-tree for huge amount of data. In this paper, we propose a parallel R-tree construction scheme based on a Hadoop framework. The proposed scheme divides the data set into a number of partitions for which local R-trees are built in parallel via Map-Reduce operations. Then the local R-trees are merged into an global R-tree that covers the whole data set. While generating the partitions, it considers the spatial distribution of the data into account so that each partition has nearly equal amounts of data. Therefore, the proposed scheme gives an efficient index structure while reducing the construction time. Experimental tests show that the proposed scheme builds an R-tree more efficiently than the existing approaches.

• 대한전자공학회논문지TC
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• 제37권1호
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• pp.54-65
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• 2000

안테나 배열을 사용하는 직접 대역 확산 시스템에서 초기 동기 포착을 위하여 안테나 배열을 사용하는 병렬 포착 방식을 제안한다. 제안된 병렬 방식은 단일 안테나를 사용하는 기존의 병렬 방식에 비하여 포착이 가능한 SNR의 범위를 크게 낮출 수 있다. 이를 위하여, 동일한 PN (pseudo-noise) 위상에 해당하는 안테나 배열로부터의 독립된 판정 변수들을 합하여 새로운 판정 변수로 사용한다. 성능분석을 위하여 부가성 백색 가우시안 잡음과 Rayleigh 페이딩 채널하에서 검출확률, 손실확룔, 오인확룔이 유도되며, 이러한 값들을 이용하여 제안된 방식의 평균 포착 성능을 평가한다. 수치적인 분석 결과를 통하여, 제안된 시스템의 성능은 안테나의 개수가 증가함에 따라 지속적으로 향상된다는 사실을 확인할 수 있다.

• ETRI Journal
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• 제32권2호
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• pp.222-229
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• 2010

A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a $2{\times}2$ multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.

• 한국정밀공학회지
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• 제16권1호통권94호
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• pp.200-209
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• 1999

This paper presents a precise tracking control scheme for the proposed parallel robot using artificial neural network. This control scheme is composed of three feedback controllers and one feedforward controller. Conventional PD controller and artificial neural network are used as feedback and feedforward controller respectively. A backpropagation learning strategy is applied to the training of artificial neural network, and PD controller outputs are used as target outputs. The PD controllers are designed at the robot dynamics based on inter-relationship between active joints and moving platform. Feedback controllers insure the total stability of system, and feedforward controller generates the control signal for trajectory tracking. The precise tracking performance of proposed control scheme is proved by computer simulation.

• 산업공학
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• 제15권4호
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• pp.338-348
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• 2002

In this paper, we present a restricted tabu search(RTS) algorithm that schedules jobs on identical parallel machines in order to minimize the maximum lateness of jobs. Jobs have release times and due dates. Also, sequence-dependent setup times exist between jobs. The RTS algorithm consists of two main parts. The first part is the MATCS(Modified Apparent Tardiness Cost with Setups) rule that provides an efficient initial schedule for the RTS. The second part is a search heuristic that employs a restricted neighborhood generation scheme with the elimination of non-efficient job moves in finding the best neighborhood schedule. The search heuristic reduces the tabu search effort greatly while obtaining the final schedules of good quality. The experimental results show that the proposed algorithm gives better solutions quickly than the existing heuristic algorithms such as the RHP(Rolling Horizon Procedure) heuristic, the basic tabu search, and simulated annealing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권1호
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• pp.31-38
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• 2016

A novel self-reference sense amplifier with parallel reading during writing operation is proposed. Read access time is improved compared to conventional self-reference scheme with fast operation speed by reducing operation steps to 1 for read operation cycle using parallel reading scheme, while large sense margin competitive to conventional destructive scheme is obtained by using self-reference scheme. The simulation was performed using standard $0.18{\mu}m$ CMOS process. The proposed self-reference sense amplifier improved not only the operation speed of less than 20 ns which is comparable to non-destructive sense amplifier, but also sense margin over 150 mV which is larger than conventional sensing schemes. The proposed scheme is expected to be very helpful for engineers for developing MRAM technology.

• 한국통신학회논문지
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• 제30권6C호
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.