• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.45-48
• /
• 2010

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.3
• /
• pp.251-260
• /
• 2002

The parallel/distributed processing with a lot of the idle hosts on the web has the high coot-performance ratio for large-scale applications. It's processing has to show the solutions for unpredictable status such as heterogeneity of hosts, variability of hosts, autonomy of hosts, the supporting performance continuously, and the number of hosts which are participated in computation and so on. In this paper, we propose the strategy of adaptive tack reallocation based on performance the host job processing, spread out geographically Also, It shows the scheme of dynamic host management with dynamic environment, which is changed by lots of hosts on the web during parallel processing for large-scale applications. This paper implements the PDSWeb (Parallel/Distributed Scheme on Web) system, evaluates and applies It to the generation of rendering image with highly intensive computation. The results are showed that the adaptive task reallocation with the variation of hosts has been increased up to maximum 90% and the improvement in performance according to add/delete of hosts.

• Journal of the Korean Society for Precision Engineering
• /
• v.20 no.4
• /
• pp.59-67
• /
• 2003

This paper presents a new approach for the use of smart materials, piezoelectric materials of PVDF and PZT, for vibration attenuation of a planar parallel manipulator. Since lightweight linkages of parallel manipulators deform under high acceleration/deceleration, an active damper is needed to attenuate vibration due to structural flexibility of linkages. Based on the dynamic model of a planar parallel manipulator, an active damping controller is developed, which consists of a PD feedback control scheme, applied to linear electrical motors, and a linear velocity feedback (L-type) scheme applied to either PVDF layer or PZT actuator(5). Simulation results show that piezoelectric materials yield good damping performance, resulting in precise manipulations of a planar parallel manipulator.

• Journal of Institute of Control, Robotics and Systems
• /
• v.6 no.1
• /
• pp.81-90
• /
• 2000

Parallel manipulator is suitable for the high precise task because it than has higher stiffness, larger load capacity and more excellent precision, due to the closed-lop structure, than serial manipulator. But the controller design for parallel manipulator is difficult because the parallel manipulator has both the complexity of structure and the interference of actuators. The precision improvement of parallel manipulator using a classical linear control scheme is difficult because the parallel manipulator has the tough nonlinear characteristics. In this paper, firstly, the kinematic analysis of a parallel manipulator used at the experiments is performed so as to show the controllability. The analysis of internal singular configuration of the workspace is performed using the kinematic isotropic index so a sto show the limitation of control performance of a simple linear controller with fixed control gains. Secondly, a control scheme is designed by using an adaptive fuzzy logic controller so that active joints of the parallel manipulator track more precisely the desired input trajectory. This adaptive fuzzy logic controller so that active joints of the parallel manipulator track more precisely the desired input trajectory. This adaptive fuzzy logic controller is often used for the control of nonlinear system because it has both the inference ability and the learning ability. Lastly, the effeciency of designed control scheme is demonstrated by the real-time control experiments with IBM PC interface logic H/W and S/W of my won making. The experimental results was a success.

• Journal of the Korea Society for Simulation
• /
• v.11 no.2
• /
• pp.67-75
• /
• 2002

This paper proposes a parallel simulation algorithm for bounded Petri nets in a single processor, which exploits the SIMD(Single Instruction Multiple Data)-type parallelism. The proposed algorithm is based on a data packing scheme which packs multiple bytes data in a single register, thereby being manipulated simultaneously. The parallelism can reduce simulation time of bounded Petri nets in a single processor environment. The effectiveness of the algorithm is demonstrated by presenting speed-up of simulation time for two bounded Petri nets.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.2
• /
• pp.497-511
• /
• 1999

Recently, many parallel processing technologies were developed, ILP(Instruction level Parallelism) processor's performance have been growed very rapidly. especially, EPIC(Explicitly Parallel Instruction computing) architectures attempt to enhance the performance in the predicated execution and speculative execution with the hardware. In this paper to improve the code scheduling possibility by applying to the characteristics of EPIC architectures, a new register allocation algorithm is proposed. And we proves that proposed register allocation algorithm is more efficient scheme than the conventional scheme when predicated execution is applied to our scheme by experiments. In experimental results, it shows much more performance enhancement, about 19% in proposed scheme than the conventional scheme. So, our scheme is verified that it is an effective register allocation method.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.3
• /
• pp.22-28
• /
• 1997

In this paper, we propose an efficient multicast addressing scheme for he self-routing multistage networks. Using only N-bit routing header an the simple hardware logic, the new scheme can efficiently provides all point-to-multipoint connections in single pass through the multistage copy networks. We also designed a hardware logic of switching element to implementation of multicasting in ATM switches are performed.

• The KIPS Transactions:PartD
• /
• v.10D no.3
• /
• pp.459-470
• /
• 2003

It is required to research on high-dimensional index structures for efficiently retrieving high-dimensional data because an attribute vector in data warehousing and a feature vector in multimedia database have a characteristic of high-dimensional data. For this, many high-dimensional index structures have been proposed, but they have so called ‘dimensional curse’ problem that retrieval performance is extremely decreased as the dimensionality is increased. To solve the problem, the cell-based filtering (CBF) scheme has been proposed. But the CBF scheme show a linear decreasing on performance as the dimensionality. To cope with the problem, it is necessary to make use of parallel processing techniques. In this paper, we propose a parallel CBF scheme which uses a horizontally-partitioned technique as declustering. In order to maximize the retrieval performance of the proposed parallel CBF scheme, we construct our parallel CBF scheme under a SN (Shared Nothing) cluster architecture. In addition, we present a data insertion algorithm, a rage query processing one, and a k-NN query processing one which are suitable for the SN cluster architecture. Finally, we show that our parallel CBF scheme achieves better retrieval performance in proportion to the number of servers in the SN cluster architecture, compared with the conventional CBF scheme.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.3
• /
• pp.1241-1250
• /
• 2018

Parallel three-phase voltage source inverters in a direct connection configuration are widely used to increase system power ratings. A zero-sequence circulating current can be generated according to the switching method; however, the zero-sequence circulating current not only distorts current, but also reduces the system reliability and efficiency. In this paper, a model predictive control scheme is proposed for parallel inverters to drive an interior permanent magnet synchronous motor with zero-sequence circulating current suppression. The voltage vector of the parallel inverters is derived to predict and control the torque and stator flux components. In addition, the zero-sequence circulating current is suppressed by designing the cost function without an additional current sensor and high-impedance inductor. Simulation and experimental results are presented to verify the proposed control scheme.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.6C
• /
• pp.442-449
• /
• 2005

In this paper, we introduce three kinds of simplified high-speed decoding algorithms for turbo product decoder. First, A parallel decoder structure, the row and column decoders operate in parallel, is proposed. Second, HAD(Hard Decision Aided) algorithm is used for early-stopping algorithm. Lastly, P-Parallel TPC decoder is a parallel decoding scheme, processing P rows and P columns in parallel instead of decoding one by one as that in the original scheme.