• 제목/요약/키워드: Parallel SOVA

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Efficient Method to Implement Max-Log-MAP Algorithm: Parallel SOVA

  • 이창우
    • 한국통신학회논문지
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    • 제33권6C호
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    • pp.438-443
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    • 2008
  • The efficient method to implement the Max-Log-MAP algorithm is proposed by modifying the conventional algorithm. It is called a parallel soft output Viterbi algorithm (SOVA) and the rigorous proof is given for the equivalence between the Max-Log-MAP algorithm and the parallel SOVA. The parallel SOVA is compared with the conventional algorithms and we show that it is an efficient algorithm implementing the modified SOVA in parallel.

On the SOVA for Extremely High Code Rates over Partial Response Channels

  • Ghrayeb, Ali
    • Journal of Communications and Networks
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    • 제5권1호
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    • pp.1-6
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    • 2003
  • In this paper, we extend the derivation of the iterative soft-output Viterbi algorithm (SOVA) for partial response (PR) channels, and modify its decoding process such that it works consistently for arbitrary high code rates, e.g., rate 64/65. We show that the modified SOVA always outperforms the conventional SOVA that appears in the literature with a significant difference for high code rates. It also offers a significant cut down in the trace-back computations. We further examine its performance for parallel and serial concatenated codes on a precoded Class IC partial response (PR4) channel. Code rates of the form $\frac{k_0}{k_0+1}$($k_0$ = 4, 8, and 64) are considered. Our simulations indicate that the loss suffered by the modified SOVA, relative to the APP algorithm, is consistent for all code rates and is at most 1.2 dB for parallel concatenations and at most 1.6 dB for serial concatenations at $P_b$ = $10^{-5}$.

대수적 구조를 가진 2단 연판정 출력 비터비 알고리듬 (A Two-Step Soft Output Viterbi Algorithm with Algebraic Structure)

  • 김우태;배상재;주언경
    • 한국통신학회논문지
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    • 제26권12A호
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    • pp.1983-1989
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    • 2001
  • 본 논문에서는 터보복호기 설계를 위하여 2단 연판정 출력 비터비 알고리듬에 대수적 구조를 적용한 대수적 (algebraic) 2단 연판정 출력 비터비 알고리듬이 제시된다. 제시된 알고리듬은 대수적 구조를 이용함으로써 행렬화된 가지(branch) 및 상태(state) 메트릭의 병렬연산이 가능하다. 띠·라서 기존의 방식에 비해 곱의 연산량이 감소되며 전체 메모리가 줄어든다. 그러므로 제시된 대수적 2단 연판정 출력 비터비 알고리듬은 적은 계산량과 단순한 하드웨어가 요구되는 터보부호의 복호기에 적합할 것으로 사료된다.

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