• Journal of Korean Society of Industrial and Systems Engineering
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• v.32 no.2
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• pp.85-93
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• 2009

GOMS model is a cognitive modeling method of human performance based on Goal, Operators, Methods, Selection rules. GOMS model was originally designed for desktop environment so that it is difficult for GOMS model to be implemented into the mobile environment. In addition, GOMS model would be inaccurate because the original GOMS model was based on serial processing, excluding one of most important human information processing characteristics, parallel processing. Therefore this study was designed to propose a modified GOMS model including mobile computing and parallel processing. In order to encompass mobile environment, an operator of 'look for' was divided into 'visual move to' and 'recognize' whereas 'point to' and 'click' were combined into 'tab.' The results showed that newly introduced operators were necessary to estimate more accurate mobile computing behaviors. In conclusion, modified-GOMS model could predict human performance more accurately than the original GOMS model in the mobile computing environment.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1997.10a
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• pp.166-169
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• 1997

For parallel processing, the compiler partitions a loaded program into a set of tasks and makes a schedule for the tasks that will minimize parallel processing time for the loaded program. Building an optimal schedule for a given set of partitioned tasks of a program has known to be NP-complete. In this paper we introduce a GA(Genetic Algorithm)-based scheduling method in which a chromosome consists of two parts of a string which decide the number and order of tasks on each processor. An additional computation is used for feasibility constraint in the chromosome. By granularity theory, a partitioned program is categorized into coarse-grain or fine-grain types. There exist good heuristic algorithms for coarse-grain type partitioning. We suggested another GA adaptive to the coarse-grain type partitioning. The infeasibility of chromosome is overcome by the encoding and operators. The number of processors are decided while the GA find the minimum parallel processing time.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.3
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• pp.163-171
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• 2013

Recently, the requirement of processing High Definition (HD) video or 3D application on low, mobile devices has been expanded and content data has been increased as well. It is becoming a major issue in Cloud computing where a Virtual Desktop Infrastructure (VDI) Service needs efficient data processing ability to provide Quality of Experience (QoE) in Cloud computing. In this paper, we propose three kind of Thick-Thin VDI Service which can share and delegate VDI service based on Thick Client using CPU and GPU. Furthermore, we propose and discuss the VDI Service Optimization Method in mixed CPU and GPU Heterogeneous Environment using CPU Parallel Processing OpenMP and GPU Parallel Processing CUDA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1168-1173
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• 2013

This paper proposes a new visualization method based on cloud technique which uses internal relationship of user correlation and external relation of social network to visualize user relationship hierarchy. The visualization method of this paper can well represent user-focused relationship hierarchy on social networks by a correlation matrix. The importance of a access node reflects into user relationship hierarchy by exploiting external relation of social network. Users of the method can well understand user relationships on account of representing user relationship hierarchy from social networks. In addition, the method use hadoop and hive for distribution storing and parallel processing which the result of calculation visualizes hierarchy graph using D3.

• Applied Microscopy
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• v.46 no.1
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• pp.6-13
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• 2016

Fluorescence lifetime imaging microscopy (FLIM) has been considered an effective technique to investigate chemical properties of the specimens, especially of biological samples. Despite of this advantageous trait, researchers in this field have had difficulties applying FLIM to their systems because acquiring an image using FLIM consumes too much time. Although analog mean-delay (AMD) method was introduced to enhance the imaging speed of commonly used FLIM based on time-correlated single photon counting (TCSPC), a real-time image reconstruction using AMD method has not been implemented due to its data processing obstacles. In this paper, we introduce a real-time image restoration of AMD-FLIM through fast parallel data processing by using Threading Building Blocks (TBB; Intel) and octa-core processor (i7-5960x; Intel). Frame rate of 3.8 frames per second was achieved in $1,024{\times}1,024$ resolution with over 4 million lifetime determinations per second and measurement error within 10%. This image acquisition speed is 184 times faster than that of single-channel TCSPC and 9.2 times faster than that of 8-channel TCSPC (state-of-art photon counting rate of 80 million counts per second) with the same lifetime accuracy of 10% and the same pixel resolution.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.31 no.3
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• pp.264-271
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• 1995

This paper presents the data parallel processing method between a PC and a micro-controller. To implement the method a dual port RAM for a real time data processing is used. In general an A/D & D/AC card is used to send or receive the data into or from the external plant and the PC does only the computation of the A/D and the D/A data because the A/D & D/AC card does not have the ability of computation. In this study, a data parallel processing method in which the PC and micro-controller own a common dual port RAM, is introduced, so that the PC can compute the A/D and D/A data and control the plant simultaneously. The PC system with a micro-controller and the common dual port RAM is designed and its effectiveness is investigated experimentally considering the performance of both the computation of data and the controlling and monitoring the external plant.

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.262-270
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• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• 전기의세계
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• v.31 no.5
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• pp.355-360
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• 1982

In numerical computation, it is desirable to access any row or column, the main diagonal, subarrays, of a matrix without any conflict for successful parallel processing. To meet this requirement special storage scheme is used for conflict-free access of necessary data. Interconnection network, which connects processing elements and processing element memory modules, is required to execute the necessary operations. In this paper we discuss the skewing method for conflict-free, access to various bit slices and single-stage interconnection networks.