• IE interfaces
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• v.9 no.2
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• pp.75-82
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• 1996

A scheduling system is developed for a parallel machine flow shop which reflects the situations of the manufacturing processes in the tire industry. The schedule is generated via simulation using heuristic rules to get satisfaction on such constraints as due dates, demands, work-in-process, process capacity, set-up times and scheduling speed. This system, constructed with relational DB, SQL and C language, consumes less than 10 minutes of PC simulation to handle real size problems.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.32-38
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• 2021

We developed an inductively coupled plasma (ICP) etcher for GaN etching using a parallel plasma electrode source with a multifunctional chuck matched to it in order for the low power consumption and low process cost in comparison with the conventional ICP system with a helical-type plasma electrode source. The optimization process condition using it for the micro light-emitting diode (µ-LED) chip fabrication was established, which is an ICP RF power of 300 W, a chuck power of 200 W, a BCl₃/Cl₂ gas ratio of 3:2. Under this condition, the mesa structure with the etch depth over 1 ㎛ and the etch angle over 75° and also with no etching residue was obtained for the µ-LED chip. The developed ICP showed the improved values on the process pressure, the etch selectivity, the etch depth uniformity, the etch angle profile and the substrate temperature uniformity in comparison with the commercial ICP. The µ-LED chip fabricated using the developed ICP showed the similar or improved characteristics in the L-I-V measurements compared with the one fabricated using the conventional ICP method

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.357-360
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• 2019

We demonstrate an alignment technology using an imprinting process on an inorganic NiOx film. The aligned nanopattern was fabricated on a silicon wafer by laser interference lithography. The aligned nano pattern was then imprinted onto the sol-gel driven NiOx film using an imprinting process at an annealing temperature of $150^{\circ}C$. After the imprinting process, parallel grooves had been formed on the NiOx film. Atomic force microscopy and water contact angle measurements were performed to confirm the parallel groove on the NiOx film. The grooves caused liquid crystal alignment through geometric restriction, similar to grooves formed by the rubbing process on polyimide. The liquid crystal cell exhibited a pretilt angle of $0.2^{\circ}$, which demonstrated homogeneous alignment.

• Geomechanics and Engineering
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• v.15 no.5
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• pp.1047-1059
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• 2018

This paper focuses on the cracking and fragmentation process in rock materials containing a pair of non-parallel flaws, which are through the specimen thickness, under vertical compression. Several numerical experiments are conducted with varying flaw arrangements that affect the initiation and tensile wing cracks, shear crack growth, and crack coalescing behaviors. To obtain realistic numerical results, a parallelized peridynamics formulation coupled with a finite element method, which is able to capture arbitrarily occurring cracks, is employed. From previous studies, crack initiation and propagation of tensile wing cracks, horsetail cracks, and anti-wing cracks are well understood along with the coalescence between two parallel flaws. In this study, the coalescence behaviors, their fragmentation sequences, and the role of an x-shaped shear band in rock material containing two non-parallel flaws are discussed in detail on the basis of simulation results strongly correlated with previous experimental results. Firstly, crack initiation and propagation of tensile wing cracks and shear cracks between non-parallel flaws are investigated in time-history and then sequential coalescing behavior is analyzed. Secondly, under the effect of varying inclination angles of two non-parallel flaws and overlapping ratios between a pair of non-parallel flaws, the cracking patterns including crack coalescence, fragmentation, and x-shaped shear band are investigated. These numerical results, which are in good agreement with reported physical test results, are expected to provide insightful information of the fracture mechanism of rock with non-parallel flaws.

• Journal of Educational Research in Mathematics
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• v.15 no.3
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• pp.273-286
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• 2005

We teach students to explore geometric figures by its properties and establish relationships between some basic figures. The concept of parallel line play very im-portant roles in such geometry learning process. In this study, 1 investigate the con-cept of parallel line we teaching in elementary school. Students have wrong concept images for parallel line, which is the result of the elementary school mathematics text books, where only typical cases for parallel line Is presented and there is no method to find if two lines is parallel or not. Therefore, we should teach explicitly students to find if two lines is parallel or not. The depth study on it is needed to develope students' geometric thought level.

• Journal of KIISE:Databases
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• v.27 no.2
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• pp.256-268
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• 2000

Multi-way spatial join is a nested expression of two or more spatial joins. It costs much to process multi-way spatial join, but there have not still reported the scheme of parallel processing of multi-way spatial join. In this paper, parallel processing of multi-way spatial join consists of parallel multi-way spatial filter and parallel spatial refinement. Parallel spatial refinement is executed by the following two steps. The first is the generation of a graph used for reducing duplication of both spatial objects and spatial operations from pairs candidate object table that are the results of multi-way spatial filter. The second is the parallel spatial refinement using that graph. Refinement using the graph is proved to be more efficient than the others. In task creation for parallel refinement, minimum duplication partitioning of the Spatial_Obicct_On_Node graph shows best performance.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.119-122
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• 2007

In this paper, we propose the method of hardware-design for the division operation of image frame-unit processing in mobile phone camera. Generally, there are two types of the data processing, which are the parallel and serial type. The parallel type makes it possible to process in realtime, but it needs significant hardware size due to many comparators and buffer memories. Compare the serial type with the parallel type, the hardware size of the serial type is smaller than the other because it uses only one comparator, but serial type is not able to process in realtime. To use the hardware resources efficiently, we employ the serial divider since frame-unit operation for image processing does not need realtime process. When compared with both in the same bit size and operating frequency, the hardware size of the serial divider is approximately in the ratio of 13 percentage compared with the parallel divider.

• Journal of Advanced Navigation Technology
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• v.25 no.4
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• pp.293-298
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• 2021

In general, the guided weapon seeker and the guided control device process the target, search, recognition, and capture information to indicate the state of the guided missile, and play a role in controlling the operation and control of the guided weapon. The signals required for guided weapons are gaze change rate, visual signal, and end-stage fuselage orientation signal. In order to process the complex and difficult-to-process missile signals of recent missiles in real time, it is necessary to increase the data processing speed of the missiles. This study showed the processing speed after applying the stop and go and inverse enumeration algorithm among the parallel algorithm methods of PINQ and comparing the processing speed of the signal data required for the guided missile in real time using the guided missile inspection program. Based on the derived data processing results, we propose an effective method for processing missile data when applying a parallel processing algorithm by comparing the processing speed of the multi-core processing method and the single-core processing method, and the CPU core utilization rate.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.85-86
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• 2001

3D parallel rasterizer on a single chip for high performance generates consistency problem. To solve this problem, 3D parallel rasterizer with consistency buffer Os proposed. This can simultaneously process a plurality of Primitives. Experimental results show 1.1-2.0x speedups using a simple model. This method can achieve high performance and cost effectiveness.