• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.68-70
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• 1996

In this paper, an efficient parallel computation method for solving large sparse systems of linear algebraic equations by using Cholesky's method in the finite element method is studied. The methods of minimizing the number of fill-ins in the factorization process of factorization are investigated for minimizing the amount of memory and computation time. The parallel programming is implemented under the PVM(Parallel Virtual Machine) environment. The method of load-distribution is studied for minimizing the computation time and the communication time.

• 한국공작기계학회논문집
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• 제13권3호
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• pp.44-52
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• 2004

This paper proposed a error compensation methodology for three-DOF translational parallel manipulator. The proposed method uses CMM (coordinate measuring machine) as metrology equipment to measure the position of end-effector. To identify the transform relationships between the coordinate system of the parallel manipulator and the CMM coordinate system, a new coordinate referencing (or coordinate system identification) technique is presented. By using this technique, accurate coordinate transformation relationships are efficiently established. According to these coordinate transformation relationships, an equation to calculate the compensating error components at any arbitrary position of the end-effector is derived. In this paper, Monte Carlo simulation method is applied to simulate the compensation process. Through the simulation results, the proposed error compensation method proves its effectiveness and feasibility.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2005년도 추계 학술대회논문집
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• pp.157-162
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• 2005

Parallel implementation and performance assessment of the grid assembly in a structured chimera grid approach is studied. The grid assembly process, involving hole cutting and searching donor, is parallelized on the PC cluster. A message passing programming model based on the MPI library is implemented using the single program multiple data(SPMD) paradigm. The coarse-grained communication is optimized with the minimized memory allocation because that the parallel grid assembly can access the decomposed geometry data in other processors by only message passing in the distributed memory system such as a PC cluster. The grid assembly workload is based on the static load balancing tied to flow solver. A goal of this work is a development of parallelized grid assembly that is suited for handling multiple moving body problems with large grid size.

• Structural Engineering and Mechanics
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• 제23권4호
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• pp.325-337
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• 2006

A hybrid structural design and optimization methodology that combines the strengths of genetic algorithms, local search techniques, and parallel computing is developed to evolve optimal truss systems in this research effort. The primary objective that is met in evolving near-optimal or optimal structural systems using this approach is the capability of satisfying user-defined design criteria while minimizing the computational time required. The application of genetic algorithms to the design and optimization of truss systems supports conceptual design by facilitating the exploration of new design alternatives. In addition, final shape optimization of the evolved designs is supported through the refinement of member sizes using local search techniques for further improvement. The use of the hybrid approach, therefore, enhances the overall process of structural design. Parallel computing is implemented to reduce the total computation time required to obtain near-optimal designs. The support of human-computer interaction during layout optimization and local optimization is also discussed since it assists in evolving optimal truss systems that better satisfy a user's design requirements and design preferences.

• 한국멀티미디어학회논문지
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• 제18권10호
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• pp.1180-1188
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• 2015

In this paper, a parallel cell contour line extraction algorithm using CUDA, which has no inner contour lines, is proposed. The contour of a cell is very important in a cell image analysis. It could be obtained by a conventional serial contour tracing algorithm or parallel morphology operation. However, the cell image has various damages in acquisition or dyeing process. They could be turn into several inner contours, which make a cell image analysis difficult. The proposed algorithm introduces a min-max coordinates table into each CUDA thread block, and removes the inner contour in parallel. It is 4.1 to 7.6 times faster than a conventional serial contour tracing algorithm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 심포지엄 논문집 정보 및 제어부문
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• pp.144-147
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• 2005

This paper is proposed an 8$\times$8 bit parallel multiplier for low power consumption. The 8$\times$8 bit parallel multiplier is used for the comparison between the proposed Low-Swing CVSL full adder with conventional CVSL full adder. Comparing tile previous works, this circuit is reduced the power consumption rate of 8.2% and the power-delay-product of 11.1%. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.35$\{\mu}m$ standard CMOS process.

• Journal of applied mathematics & informatics
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• 제33권1_2호
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• pp.77-87
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• 2015

Parallel lines are often used to increase production rate in many manufacturing systems where the main line splits into several lines in parallel, and after some operations, they merge into a main line again. Queueing networks with finite buffers have been widely used for modeling and analyzing manufacturing systems. This paper provides an approximation technique for multi-server two-stage networks with merge configuration and blocking which will be a building block for analysis of general manufacturing systems with parallel lines and merge configuration. The main idea of the method is to decompose the original system into subsystems that have two service stations with multiple servers, two buffers and external arrivals to the second stage are allowed. The subsystems are modeled by level dependent quasi-birth-and-death (LDQBD) process.

• 산업기술연구
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• 제21권A호
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• pp.73-80
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• 2001

Barrier is widely used for synchronization in parallel programs. Since the process arrived earlier than others should wait at the barrier, the total processor utilization decreases. In this paper, to find the sources of the barrier waiting time, parallel programs are executed on the various grain sizes through execution-driven simulations. In simulation studies, we found that even if approximately equal amounts of work are distributed to each processor, all processes may not arrive at a barrier at the same time. The reasons are that the different numbers of cache misses and instructions within partitioned grains result in the difference in arrival time of processors at the barrier.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 추계학술대회논문집A
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• pp.818-823
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• 2000

In practical design studies, most of designers solve multidisciplinary problems with complex design structure. These multidisciplinary problems have hundreds of analysis and thousands of variables. The sequence of process to solve these problems affects the speed of total design cycle. Thus it is very important for designer to reorder original design processes to minimize total cost and time. This is accomplished by decomposing large multidisciplinary problem into several multidisciplinary analysis subsystem (MDASS) and processing it in parallel. This paper proposes new strategy for parallel decomposition of multidisciplinary problem to raise design efficiency by using genetic algorithm and shows the relationship between decomposition and multidisciplinary design optimization (MDO) methodology.

• 대한전기학회논문지
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• 제39권10호
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• pp.1057-1065
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• 1990

A parallel processing algorithm for the discrete Kalman filter, which is one of the most commonly used filtering techniques in modern control, signal processing, and communication, is proposed. To decrease the number of computations critical in the Kalman filter, previously proposed parallel algorithms are of the hierarchical structure by distributed processing of measurements, or of the systolic structure to disperse the computational burden. In this paper, a new parallel Kalman filter employing a structure similar to recursive doubling is proposed. Estimated valuse of state variables by the new algorithm converge faster to the true values because the new algorithm can process data twice faster than the conventional Kalman filter. Moreover, it maintains the optimality of the conventional Kalman filter.