• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1601-1610
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• 2011

This paper discusses standardization activities, requirements and enabling technologies for 100G Ethernet and 100G OTN. The need of 100Gbps transport capacity has been gaining greater interest from service providers and carrier vendors. Moreover, optical transport networks based on OTN/DWDM are changing their properties to apply Ethernet traffic which is dramatically increasing. We realize and experimentally demonstrate OTU4 framer with commercial FPGA. The key features of the realized OTU4 framer are parallel signal processing function, multi-lane distribution function, GMP function and FEC function. The realized OTU4 framer has the large signal processing capacity of 120Gbps, which allows to transport about 120Gbps client signals such as $12{\times}10G$ Ethernet and $3{\times}40G$ Ethernet. The realized OTU4 framer has the advantages to quickly adjust to changing markets and new technologies by using commercial FPGA instead of ASIC.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.585-589
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• 2016

Recently, the robotic assist system for cardiovascular intervention gets continuously growing interest. The robotic cardiovascular intervention systems are largely two folds, systems for cardiac ablation procedure assist and systems for vascular intervention assist. For the systems, the clinician controls the catheter inserted through blood vessel to the heart via a master console or master manipulator. Most of the current master manipulators have structure of joystick-like pivoting 2 degree of freedom (DOF) handle in the core, which is used in parallel with other sliding switches and input devices. It however is desirable to have customized and optimized design manipulator that can provide clinician with intuitive control of the catheter motion fully utilizing the advantage of the use of robotic structure. A 6 DOF kinematic mechanism that can capture the motion control intention of the clinician in translational 3 DOF and rotational 3 DOF is proposed in this paper. Also, a master-slave motion relationship specially designed for the cardiac catheter manipulation motion is proposed and implemented in an experimental prototype. Design revision for implementation of more efficient motion and experiment in combination with an experimental slave robot system for catheter manipulation are underway.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.186-192
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• 2009

PID controllers are simple in structure and easy for implementation. However, they may produce large overshoots and over-oscillatory responses. Combining PID control with other control techniques often results in advanced hybrid schemes that are able to improve pure PID controllers. This paper proposes hybrid controller for position control system of servo motor. The proposed controller is composed of a subcontroller and a parallel PID controller. The subcontroller improves the transient system performance while the PID controller is mainly responsible for the steady-state system performance. A very promising advantage of this hybrid scheme, in terms of controller synthesis, is that the subcontrollers and controller components can be designed separately. Systematic design methods for various controller components are developed. The proposed hybrid scheme is applied to a DC motor position servo system. The effectiveness of the proposed controller is verified through the computer simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.5
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• pp.333-340
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• 2003

Doppler processing is the heart of pulsed Doppler radar. It gives a clutter elimination and coherent integration. With the improvement of digital signal processors (DPSs), the implementation using them is more widely used in radar systems. Generally, so as for Doppler processor to process the input data in real time, a parallel processing concept using multiple DSPs should be used. This paper implements a programmable Doppler processor, which consists of MTI filter, DFB and square-law detector, using 8 ADSP21060s. Formulating the distribution time of the input data, the transfer time of the output data and the time required to compute each algorithm, it estimates total processing time and the number of required DSP. Finally, using the TSG that provides radar control pulses and simulated target signals, performances of the implemented Doppler processor are evaluated.

• International Journal of Concrete Structures and Materials
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• v.11 no.2
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• pp.343-363
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• 2017

The objective of this work was finding out the most advisable testing conditions for an effective and robust characterization of the tensile strength (TS) of concrete disks. The independent variables were the loading geometry, the angle subtended by the contact area, disk diameter and thickness, maximum aggregate size, and the sample compression strength (CS). The effect of the independent variables was studied in a three groups of experiments using a factorial design with two levels and four factors. The likeliest location where failure beginning was calculated using the equations that account for the stress-strain field developed within the disk. The theoretical outcome shows that for failure beginning at the geometric center of the sample, it is necessary for the contact angle in the loading setup to be larger than or equal to a threshold value. Nevertheless, the measured indirect tensile strength must be adjusted to get a close estimate of the uniaxial TS of the material. The correction depends on the loading geometry, and we got their mathematical expression and cross-validated them with the reported in the literature. The experimental results show that a loading geometry with a curved contact area, uniform load distribution over the contact area, loads projected parallel to one another within the disk, and a contact angle bigger of $12^{\circ}$ is the most advisable and robust setup for implementation of BT on concrete disks. This work provides a description of the BT carries on concrete disks and put forward a characterization technique to study costly samples of cement based material that have been enabled to display new and improved properties with nanomaterials.

• Journal of IKEEE
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• v.24 no.1
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• pp.225-231
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• 2020

In this paper, we propose a method to accelerate BWN based on FPGA with limited resources for embedded system. Because of the limited number of logic elements available, a single computing unit capable of handling Conv-layer, FC-layer of various sizes must be designed and reused. Also, if the input feature map can not be parallel processed at one time, the output must be calculated by reading the inputs several times. Since the number of available BRAM modules is limited, the number of data bits in the BWN accelerator must be minimized. The image classification processing time of the BWN accelerator is superior when compared with a embedded CPU and is faster than a desktop PC and 50% slower than a GPU system. Since the BWN accelerator uses a slow clock of 50MHz, it can be seen that the BWN accelerator is advantageous in performance versus power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.59-70
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• 2007

In this paper, we proposed an effective T&L(Transform & Lighting) Processor architecture for a real time 3D graphics acceleration SoC(System on a Chip) in a mobile system. We designed Floating point arithmetic IPs for a T&L processor. And we verified IPs using a SoC Platform. Designed T&L Processor consists of 24 bit floating point data format and 16 bit fixed point data format, and supports the pipeline keeping the balance between Transform process and Lighting process using a parallel computation of 3D graphics. The delay of pipeline processing only Transform operation is almost same as the delay processing both Transform operation and Lighting operation. Designed T&L Processor is implemented and verified using a SoC Platform. The T&L Processor operates at 80MHz frequency in Xilinx-Virtex4 FPGA. The processing speed is measured at the rate of 20M Vertexes/sec.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.469-479
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• 2009

The GEM frame is used a mean to deliver the variable length user data and consists of the header and the payload in the G-PON system. The HEC field of header protects contents of the header and is used to maintain GEM frame synchronization at the same time. When an LCDG (Loss of GEM Channel Delineation) occurs while receiving frames, the receiver have to discard corrupted frames until acquiring the synchronization again. Accordingly, high-speed synchronization method is required to minimize the frame loss. In this paper, we suggest not only a main state machine but a sub-state machine to reduce the frame loss when undetectable errors occurred in the GEM header. Also, we provide a more efficient and fast parallel structure to detect the starting point of the header. Finally, the proposed method is implemented with the FPGA and verified by the logic analyzer.