• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.50-59
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• 2000

Stereo vision is a technique extracting depth information from stereo images, which are two images that view an object or a scene from different locations. The most important procedure in stereo vision, which is called stereo matching, is to find the same points in stereo images. It is difficult to match stereo images in real time because stereo matching requires heavy calculation. In this Paper we design a digital VLSI to Process stereo matching in real time, which we call stereo image match processor (SIMP). For implementation of real time stereo matching, sliding memory and minimum selection tree are presented. SIMP is designed with pipeline architecture and parallel processing. SIMP takes 64 gray level 64$\times$64 stereo images and yields 8 level 64 $\times$64 disparity map by 3 bit disparity and 12 bit address outputs. SIMP can process stereo images with process speed of 240 frames/sec.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The Journal of Korean Association of Computer Education
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• v.11 no.3
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• pp.81-89
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• 2008

The failure occurrence of resources in the grid computing is higher than in a tradition parallel computing. Since the failure of resources affects job execution fatally, fault tolerance service is essential in computational grids. And grid services are often expected to meet some minimum levels of quality of service (QoS) for desirable operation. However Globus toolkit does not provide fault tolerance service that supports fault detection service and management service and satisfies QoS requirement. Thus this paper proposes fault tolerance service to satisfy QoS requirement in computational grids. In order to provide fault tolerance service and satisfy QoS requirements, we expand the definition of failure, such as process failure, processor failure, and network failure. And we propose resource scheduling service, fault detection service and fault management service and show implement and experiment results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1180-1192
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• 1996

On demand of many users, basic networks of a parallel computer system are required to have a property that can embed various topologies. Bisectional interconnection network is known to satisfy this property, and it can embed various topologies optimally. Nowadays one is very interested in the hypercube as a message pssing multicomputer system, so it is very important to implement a hypercube in bisectional network. In this paper, a hypercube is implemented in a versatile bisecional netork, and its routing and broadcasting algorithm are proposed. Conventional bisectional network can accomodata linear array, complete binary tree and mesh structure as its topology. Now hypercube is implemented to be utilized as a general purpose supercomputercommunication architecture. The proposed routing and broadcasting algorithm embedded in bisectional network are general purpose algorithms which satisfy property of conventional hypercube.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12B
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• pp.758-766
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• 2007

IStreaming services with a client-server architecture have scalability problem because a server cannot accomodate clients more than its processing capability. This paper introduces a case study for implementing H.264 streaming system based on P2P architecture in order to provide scalable and stable broadcast streaming services over the internet. The prototype system called OmniCast264 consists of the H.264 encoding server, the streaming server, the proxy server, and peer nodes. The proxy server dynamically manages placement of the peer nodes on the P2P network. Omnicast264 has the concepts of distributed streaming loads, real-time playback, error-robustness and modularity. Thus, it can provide large-scale broadcast streaming services. Finally, we have built P2P streaming systems with 12 PCs connected serially or in parallel. The experiment shows that OmniCast264 can provide real-time playback.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.64-71
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• 2009

This paper presents an efficient frame synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation(DVB-S2). To achieve the satisfactory performance under severe channel conditions and the efficient hardware resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can improve the performance of the frame and frequency synchronizer since each block operates jointly in parallel and significantly reduce the complexity of the frame synchronizer. Hence, The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&STM SFU broadcast test equipment and consists of 29,821 LUTs with XilinxTM Virtex IV LX200.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.23-30
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• 2009

In this paper, the intelligent vision system for an effective and intelligent path-planning of an industrial AGV system based on stereo camera system is proposed. The depth information and disparity map are detected in the inputting images of a parallel stereo camera. The distance between the industrial AGV system and the obstacle detected and the 2D Path coordinates obtained from the location coordinates, and then the relative distance between the obstacle and the other objects obtained from them. The industrial AGV system move automatically by effective and intelligent path-planning using the obtained 2D path coordinates. From some experiments on AGV system driving with the stereo images, it is analyzed that error ratio between the calculated and measured values of the distance between the objects is found to be very low value of 2.5% on average, respectably.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.63-70
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• 2004

This paper describes the link layer and physical layer of the Serial ATA which is the next generation for parallel ATA specification that defines data transfer between PC and peripheral storage devices. The link layer consists of CRC generation/error detection, 8b/10b decoding/encoding, primitive generation/detection block. For the physical layer, it includes CDR(Cock Data Recovery), transmission PLL, serializer/de-serializer. It also includes generation and receipt of OOB(Out-Of-Band) signal, impedance calibration, squelch circuit and comma detection/generation. Additionally, this chip includes TCB(Test Control Block) and BIST(Built-In Selt Test) block to ease debugging and verification. It is fabricated with 0.18${\mu}{\textrm}{m}$ standard CMOS cell library. All the function of the link layer operate properly. For the physical layer, all the blocks operate properly but the data transfer is limited to the 1.28Gbps. This is doe to the affection or parasitic elements and is verified with SPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.509-516
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• 2004

High-performance Si integrated passive process was developed using thick oxidation process and Cu-BCB process. This passive process leads to low-cost and high-quality RF module with a small form factor. The fabricated spiral inductor with 225 um inner diameter and 2.5 turns showed the inductance of 2.7 nH and the quality factor more than 30 in the frequency region of 1 ㎓ and above. Also WLCSP-type integrated passive devices were fabricated using the high-performance spiral inductors. The fabricated low pass filter had a parallel-resonance circuit inside the spiral inductor to suppress 2nd harmonics and showed about 0.5 ㏈ insertion loss at 2.45 ㎓. And also the high/low-pass balun had the insertion loss less than 0.5 ㏈ and the phase difference of 182 degrees at 2.45 ㎓.

• Journal of Broadcast Engineering
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• v.13 no.6
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• pp.859-874
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• 2008

In this paper, we develop a fast view synthesis method that generates multiple intermediate views in real-time for the 3D display system when the camera geometry and depth map of reference views are given in advance. The proposed method achieves faster view synthesis than previous approaches in GPU by processing in parallel the entire computations required for the view synthesis. Specifically, we use $CUDA^{TM}$ (by NVIDIA) to control GPU device. For increasing the processing speed, we adapted all the processes for the view synthesis to single instruction multiple data (SIMD) structure that is a main feature of CUDA, maximized the use of the high-speed memories on GPU device, and optimized the implementation. As a result, we could synthesize 9 intermediate view images with the size of 720 by 480 pixels within 0.128 second.