• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.187-194
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• 2005

In this paper, an efficient and fast algerian to reduce calculation amount of FIR(Finite Impulse Responses) filtering is proposed. Proposed algorithm enables arbitrary size of parallel processing, and their structures are also easily derived. Furthermore, it is shown that the number of multiplication/sample is reduced, and number of instructions using MAC(Multiplication and Accumulation) processor are also reduced. For theoretical improvement numbers of sub filters are compared with those of conventional algorithm. In addition to the theoretical improvement, it is shown that number of element for hardwired implementation are reduced comparison to those of the conventional algorithm.

• Journal of IKEEE
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• v.20 no.3
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• pp.303-306
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• 2016

In this paper, we propose a method to accelerate convolutional neural network by utilizing a GPGPU. Convolutional neural network is a sort of the neural network learning features of images. Convolutional neural network is suitable for the image processing required to learn a lot of data such as images. The convolutional layer of the conventional CNN required a large number of multiplications and it is difficult to operate in the real-time on the embedded environment. In this paper, we reduce the number of multiplications through Winograd convolution operation and perform parallel processing of the convolution by utilizing SIMT-based GPGPU. The experiment was conducted using ModelSim and TestDrive, and the experimental results showed that the processing time was improved by about 17%, compared to the conventional convolution.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2
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• pp.38-49
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• 1994

This paper proposes Echo canceller used in simultaneous two-way ('full-duplex') transmission of data signals over two-wire circuits which can be achieved by using a hybrid coupler. This Echo canceller uses sequential processing instead of parallel processing with conventional adaptive digital filter. This structure reduces the number of multipliers. Thus, this structure is much more suitable for IC implementation. This Echo canceller operates according to the 'Stochastic Iteration Algorithm(SIA).' SIA algorithm has merit of good performance and small hardware requirement.

• Convergence Security Journal
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• v.19 no.3
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• pp.21-28
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• 2019

As the number of websites managed by organizations or organizations increases, so does the number of web application servers and containers. In checking the status of the web service of the web application server and the container, it is very difficult for the person to check the status of the web service after accessing the physical server at the remote site through the terminal or using other accessible software It. Previous research on crawler-related research is hard to find any reference to the processing of data from crawling. Data loss occurs when the crawler accesses the database and stores the data. In this paper, we propose a method to store the inspection data according to crawl - based web application server management without losing data.

• KSBB Journal
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• v.22 no.6
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• pp.387-392
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• 2007

Recently, microfluidic biochips for DNA microarray are providing a number of advantages such as, reduction in reagent volume, high-throughput parallel sample screening, automation of processing, and reduction in hybridization time. Particularly, the enhancement of target probe hybridization by decrease of hybridization time is an important aspect highlighting the advantage of microfluidic DNA microarray platform. Fundamental issues to overcome extremely slow diffusion-limited hybridization are based on physical, electrical or fluidic dynamical mixing technology. So far, there have been some reports on the enhancement of the hybridization with the microfluidic platforms. In this review, their principle, performance, and outreaching of the technology are overviewed and discussed for the implementation into many bio-applications.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.319-323
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• 2003

In this paper, we propose a hybrid transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater channel environments. It is designed in the digital domain except for amplifiers and implemented by using a multiple digital signal processors (DSPs) system. The digital modulation technique is quadrature phase shift keying (QPSK) and frame synchronization is an energy (non-coherent) detection scheme based on the quadrature receiver structure. DSP implementation is based on block data parallel architecture (BDPA). We shaw experimental results in th? underwater anechoic basin at KRISO. The results indicate that the frame synchronization is performed without PLL. Also, we shaw that the adaptive equalizer can compensate frame synchronization error and the correction capability is dependent on the length of equalizer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.9
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• pp.512-519
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• 2000

A Neural networks has been used for a expert system and fault diagnosis system. It is possible to nonlinear function mapping and parallel processing. Therefore It has been developing for a Diagnosis system of nuclear plower plant. In general Neural Networks is a static mapping but Dynamic Neural Network(DNN) is dynamic mapping.쪼두 a fault occur in system a state of system is changed with transient state. Because of a previous state signal is considered as a information DNN is better suited for diagnosis systems than static neural network. But a DNN has many weights so a real time implementation of diagnosis system is in need of a rapid network architecture. This paper presents a algorithm for RCP monitoring Alarm diagnosis system using Self Dynamic Neural Network(SDNN). SDNN has considerably fewer weights than a general DNN. Since there is no interlink among the hidden layer. The effectiveness of Alarm diagnosis system using the proposed algorithm is demonstrated by applying to RCP monitoring in Nuclear power plant.

• Journal of Power Electronics
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• v.14 no.4
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• pp.733-741
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• 2014

The integration of photovoltaic (PV) energy sources into DC grid has gained considerable attention because of its enhanced conversion efficiency with reduced number of power conversion stages. During the integration process, a local control unit is normally included with every power conversion stage of the PV source to accomplish the process of maximum power point tracking. A centralized monitoring and supervisory control unit is required for monitoring, power management, and protection of the entire system. Therefore, we propose a field-programmable gate array (FPGA) based centralized control unit that integrates all local controllers with the centralized monitoring unit. The main focus of this study is on the process of integrating many local control units into a single central unit. In this paper, we present design and optimization procedures for the hardware implementation of FPGA architecture. Furthermore, we propose a transient analysis and control design methodology with consideration of the nonlinear characteristics of the PV source. Hardware experiment results verify the efficiency of the central control unit and controller design.

• The Transactions of the Korea Information Processing Society
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• v.4 no.8
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• pp.1987-1994
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• 1997

ATM switching software should be required high reliability, functionality, extendability and maintainability. After development of the software, it is verified and tested by analyzer whether the software is accomplished the characteristics of it or not. There are so many CASE tools in other area, but the CHILL testing tools that can verify ATM softwares have not various functions are not many. In this paper we develop the testing tool which can evaluate and test CHILL programmed ATM software. This Tool supports testing reports, debugging informations and maintenance informations including parallel process about CHILL original programs.