• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.3
• /
• pp.67-74
• /
• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• ETRI Journal
• /
• v.30 no.3
• /
• pp.347-354
• /
• 2008

In this paper, the design of a low-power 512-bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low-power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage-up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 ${\mu}m$ EEPROM process. Power dissipation is 32.78 ${\mu}W$ in the read cycle and 78.05 ${\mu}W$ in the write cycle. The layout size is 449.3 ${\mu}m$ ${\times}$ 480.67 ${\mu}m$.

• Journal of Korea Multimedia Society
• /
• v.4 no.1
• /
• pp.82-90
• /
• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• Journal of the Korean Society for Precision Engineering
• /
• v.20 no.5
• /
• pp.218-224
• /
• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.175-183
• /
• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.6
• /
• pp.1115-1122
• /
• 2003

In this paper we fabricated microchip antenna operating in bluetooth frequency bands(2.402∼2.480GHz). The antenna has a size of about 54mm${\times}419mm${\times}40.8mm, giving a total bluetooth PCB for support and chip of about 11mm${\times}44mm${\times}41.6mm. Bandwidth of the designed and fabricated chip antenna for bruetooth is 10.71 % at the resonated frequency of 2.45GHz and the resonant frequency and bandwidth versus change of any arbitrary feed point is observed. also, E-plane and H-plane in the Measured radiation pattern characteristic of chip antenna is compared and analyzed.

• KSBB Journal
• /
• v.16 no.6
• /
• pp.538-546
• /
• 2001

An integrated data analysis program for DNA chip containing normalization, FDM analysis, various kinds of clustering methods, PCA, and SVD was applied to analyze combined yeast cell cycle data. This paper includes both comparisons of some clustering algorithms such as K-means, SOM and furry c-means and their results. For further analysis, clustering results from the integrated analysis program was used for function assignments to each cluster and for motif analysis. These results show an integrated analysis view on DNA chip data.

• Journal of Sensor Science and Technology
• /
• v.17 no.1
• /
• pp.15-22
• /
• 2008

When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1282-1287
• /
• 2005

The accuracy of chip alignment in inferior product inspection of COG(Chip On Glass) to be measured a few micro unit is very important role since the accuracy of chip inspection depends on chip alignment. In this paper, we propose the area segmentation pattern matching method to enhance the accuracy of chip alignment. The area segmentation pattern matching method compares, and matches correlation coefficients between the characteristic features within the detailed area and the areas. The three areas of pattern circumference are learned to minimize the matching error by bad pattern. The proposed method has advantage such as reduction of matching time, and enhanced accuracy since the characteristic features are searched within the segmented area.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.10 no.3
• /
• pp.270-279
• /
• 2000

This paper describes the on-chip learning algorithm of neural networks using the stochastic pulse arithmetic. Stochastic pulse arithmetic is the computation using the numbers represented by the probability of 1' and 0's occurrences in a random pulse stream. This stochastic arithmetic has the merits when applied to neural network ; reduction of the area of the implemented hardware and getting a global solution escaping from local minima by virtue of the stochastic characteristics. And in this study, the on-chip learning algorithm is derived from the backpropagation algorithm for effective hardware implementation. We simulate the nonlinear separation problem of the some character patterns to verify the proposed learning algorithm. We also had good results after applying this algorithm to recognize printed and handwritten numbers.