• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.470-480
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• 2016

The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical silicon-surface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.2
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• Biotechnology and Bioprocess Engineering:BBE
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• v.9 no.2
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• pp.100-106
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• 2004

Micro-fluidics is one of the major technologies used in developing micro-total analytical systems (${\mu}$-TAS), also known as “lab-on-a-chip”. With this technology, the analytical capabilities of room-size laboratories can be put on one small chip. In this paper, we will briefly introduce materials that can be used in micro-fluidic systems and a few modules (mixer, chamber, and sample prep. modules) for lab-on-a-chip to analyze biological samples. This is because a variety of fields have to be combined with micro-fluidic technologies in order to realize lab-on-a-chip.

• ETRI Journal
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• v.27 no.5
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• pp.563-568
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• 2005

A motion-control chip contains major functions that are necessary to control the position of each motor, such as generating velocity command profiles, reading motor positions, producing control signals, driving several types of servo amplifiers, and interfacing host processors. Existing motion-control chips can only generate velocity profiles of fixed characteristics, typically linear and s-shape smooth symmetric curves. But velocity profiles of these two characteristics are not optimal for all tasks in industrial robots and automation systems. Velocity profiles of other characteristics are preferred for some tasks. This paper proposes a motion-control chip to generate velocity profiles of desired acceleration and deceleration characteristics. The proposed motion-control chip is implemented with a field-programmable gate array by using the Very High-Speed Integrated Circuit Hardware Description Language and Handel-C. Experiments using velocity profiles of four different characteristics will be performed.

• Journal of Korea Multimedia Society
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• v.19 no.2
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• pp.352-359
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• 2016

This paper presents high efficiency 5A synchronous DC-DC buck converter. The proposed DC-DC buck converter works from 4.5V to 18V input voltage range, and provides up to 5A of continuous output current and output voltage adjustable down to 0.8V. This chip is packaged MCP(multi-chip package) with control chip, top side P-CH switch, and bottom side N-CH switch. This chip is designed in a 25V high voltage CMOS 0.35um technology. It has a maximum power efficiency of up to 94% and internal 3msec soft start and fixed 500KHz PWM(Pulse Width Modulation) operations. It also includes cycle by cycle current limit function, short and thermal shutdown protection circuit at 150℃. This chip size is 2190um*1130um includes scribe lane 10um.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• KSBB Journal
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• v.25 no.4
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• pp.344-350
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• 2010

This paper demonstrates a microfluidic chip incorporating patterned hollow silica beads that can be effectively used for chemotaxis assay. The hollow silica bead has been exploited to develop a carrier for chemoattractant to induce cell migration. The microfluidic chip contains a patterned array of microfabricated docks which can hold only one bead per docking site. The hollow bead placed inside microfluidic chip releases chemotactic reagent (PDGF-BB) around its periphery in a controlled fashion which generates a signal for chemotatic migration of fibroblast cells. The number of cells migrated close to each bead has been assessed. On-chip cell migration assay showed a remarkable result proving the high efficiency and reliable accuracy in quantitative analysis. Therefore, the device could be extensively used in cell migration assay and other various studies related to cellular movements.

• Journal of Sensor Science and Technology
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• v.18 no.1
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• pp.42-47
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• 2009

In this paper we propose a microfluidic chip that measures the mechanical stiffness of cell membrane using impedance measurement. The microfluidic chip is composed of PDMS channel and a glass substrate with electrode. The proposed device uses patch-clamp technique to capture and deform a target cell and measures impedance of deformed cells. We demonstrated that the impedance increased after the membrane stretched and blocked the channel.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.12
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• pp.1228-1235
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• 2014

Input impedance of UHF RFID tag chip is needed to design a tag. In determining the chip impedance, direct measurement method is adopted commonly. In this paper, problems generated from fixtures that interface between tag chip and coaxial-oriented measurement instrument are investigated and the result of the problems is shown, when the direct measurement method is applied. As an alternative to the method, a modeling method is proposed and its validity and accuracy are shown.