• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.469-478
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• 2001

In the virtual memory system, page replacement policy exerts a great influence on the performance of demand paging. There are LRU(Least Recently Used) and LFU (Least Frequently Used) as the typical replacement policies. The LRU policy performs effectively in many cases and adapts well to the changing workloads compared to other policies. It however cannot distinguish well between frequently and infrequently referenced pages. The LFU policy requires that the page with the smallest reference count be replaced. Though it considers all the references in the past, it cannot discriminate between references that occurred far back in the past and the more recent ones. Thus, it cannot adapt well to the changing workload. In this paper, we first analyze memory reference patterns of eight applications. The patterns show that the recently referenced pages or the frequently referenced pages are accessed continuously as the case may be. So it is rather hard to optimize page replacement scheme by using just one of the LRU or LFU policy. This paper makes an attempt to combine the advantages of the two policies and proposes a new page replacement policy. In the proposed policy, paging list is divided into two lists (LRU and LFU lists). By keeping the two lists in recency and reference frequency order respectively, we try to restrain the highly referenced pages in the past from being replaced by the LRU policy. Results from trace-driven simulations show that there exists points on the spectrum at which the proposed policy performs better than the previously known policies for the workloads we considered. Especially, we can see that our policy outperforms the existing ones in such applications that have reference patterns of re-accessing the frequently referenced pages in the past after some time.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.426-433
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• 2003

Management policies of Web Proxy Cache, for the QoS of Web users, are mainly focused on the page replacement and the data consistency policy. But the two subjects have been studied independently to each other regardless of its possibility of cooperation. In this paper, we introduce the performance improvement obtained by adapting the characteristic of LMF used in data consistency policy to LRU, thus taking the better performance synergy as a result of complementary cooperation. Various policies for the management of Web Proxy Cache are in progress, this study can be a way of performance guide to increase cache hit ratio and reduce the transmission overhead of Web Server.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.1-10
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• 2020

In this paper, we propose an efficient disk buffer replacement policy which improves hit ratio and reduces writing operations of flash based storages. The flash based storage has many advantages, including a small form factor, non-volatility and high reliability, but there are problems caused by own limitations, like not-in-place update, short life cycle and asymmetric I/O latencies. To redeem these problems, this paper proposes the write weighted probability of reference(2WPR) policy. 2WPR policy predicts re-referencing probability and calculates localities of each page. Furthermore, by weighting write operations to every pages, 2WPR can reduce write operations to flash based storage. In addition, we can improve the performance with higher hit ratio and reduce the number of write operations and consequently shorten the latencies of each operation. The results show that our policy provides improvements of up to 10% for the hit ratio with the reduction of up to 5% for the flash writing operation compared with other policies.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.538-540
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• 2001

클러스터 시스템의 각 노드에 존재하는 메모리들을 효율적으로 관리하기 위하여 네트워크 메모리의 개념이 등장하였으며 빈번하게 디스크를 접근하는 응용분야에서 속도 향상을 위해 사용될 수 있다. 이는 전통적인 메모리 계층(hierarchy) 구조인 메모리와 디스크 사이에 네트워크 메모리를 추가함으로써 얻어진다. 본 논문에서는 웹 서버 클러스터를 대상으로 문서의 접근 유형에 대한 사전의 정보를 요구하지 않고 실제적으로 구현 가능하며 다양한 웹 문서 접근 확률 분포 값에 대하여 항상 우수한 사용자 응답시간을 가지는 메모리 관리 기법을 제안하고 시뮬레이션을 통해 제안된 방식의 우수성을 검증하였다.

• The KIPS Transactions:PartD
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• v.16D no.6
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• pp.825-834
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• 2009

최근에 낸드 플래시 메모리는 빠른 접근속도, 저 전력 소모, 높은 내구성 등의 특성으로 인하여 차세대 대용량 저장 매체로 각광 받고 있다. 그러나 디스크 기반의 저장 장치와는 달리 비대칭적인 읽기, 쓰기, 소거 연산의 처리 속도를 가지고 있고 제자리 갱신이 불가능한 특성을 가지고 있다. 따라서 디스크 기반 시스템의 버퍼 교체 정책은 플래시 메모리 기반의 시스템에서 좋은 성능을 보이지 않을 수 있다. 이러한 문제를 해결하기 위해 플래시 메모리의 특성을 고려한 새로운 플래시 메모리 기반의 버퍼 교체 정책이 제안되어 왔다. 본 논문에서는 디스크 기반의 저장 장치에서 우수한 성능을 보인 CLOCK-Pro를 낸드 플래시 메모리의 특성을 고려하여 개선한 CLOCK-NAND를 제안한다. CLOCK-NAND는 CLOCK-Pro의 알고리즘에 기반하며, 추가적으로 페이지 접근 정보를 효율적으로 활용하기 위한 새로운 핫 페이지 변경을 한다. 또한, 더티인 핫 페이지에 대해 콜드 변경 지연 정책을 사용하여 쓰기 연산을 지연하며, 이러한 새로운 정책들로 인하여 낸드 플래시 메모리에서 쓰기 연산 횟수를 효율적으로 줄이는 우수한 성능을 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.