• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.11C
• /
• pp.1171-1177
• /
• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.4
• /
• pp.1442-1462
• /
• 2014

Packet classification is a key technology of the Internet for routers to classify the arriving packets into different flows according to the predefined rulesets. Previous packet classification algorithms have mainly focused on search speed and memory usage, while overlooking update performance. In this paper, we propose PreCuts, which can drastically improve the update speed. According to the characteristics of IP field, we implement three heuristics to build a 3-layer decision tree. In the first layer, we group the rules with the same highest byte of source and destination IP addresses. For the second layer, we cluster the rules which share the same IP prefix length. Finally, we use the heuristic of information entropy-based bit partition to choose some specific bits of IP prefix to split the ruleset into subsets. The heuristics of PreCuts will not introduce rule duplication and incremental update will not reduce the time and space performance. Using ClassBench, it is shown that compared with BRPS and EffiCuts, the proposed algorithm not only improves the time and space performance, but also greatly increases the update speed.

• Proceedings of the IEEK Conference
• /
• 2000.11a
• /
• pp.307-310
• /
• 2000

ATM is the switching and multiplexing technology chosen by the ITU-T for the operation of B-lSDN. Basically, ATM technology is designed to combine the reliability of circuit switching with the efficiency and flexibility of packet switching technology. For servicing QoS in IPOA(IP over ATM) when the larger effort is given, it will be the good method that the original QoS benefits having ATM switching have in ATM layer underlying layer. The IETF has recently proposed Differentiated Services framework for provision of QoS. In this paper we analyse performance of two Diffserv mechanism. Threshold Dropping and Priority Scheduling. Threshold Dropping and Priority Scheduling can be regarded as basic mechanisms from which the other mechanisms have been derived. Hence comparative performance of these two mechanisms in providing required QoS is an important issue. In this Paper we carry out a performance comparison of the TD and PS mechanisms with the aim of providing the same level of packet loss to the preferred flow. Our comparison of the TD and PS allows us to determine resultant packet loss for the non-preferred flows as a function of various parameters of the two mechanisms.

• Proceedings of the Korean Operations and Management Science Society Conference
• /
• 1995.04a
• /
• pp.729-738
• /
• 1995

We consider a priority-based packet-switching system with three phases of the packet transmission time. Each packet belongs to one of several priority classes, and the packets of each class arrive at a switch in a Poison process. The switch transmits queued packets on a priority basis with three phases of preemption mechanism. Namely, the transmission time of each packet consists of a preemptive-repeat part for the header, a preemptive-resume part for the information field, and a nonpreemptive part for the trailer. By an exact analysis of the associated queueing model, we obtain the Laplace-Stieltjes transform of the distribution function for the delay, i.e., the time from arrival to transmission completion, of a packet for each class. We derive a set of equations that calculates the mean response time for each class recursively. Based on this result, we plot the numerical values of the mean response times for several parameter settings. The probability generating function and the mean for the number of packets of each class present in the system at an arbitrary time are also given.

• Journal of the Optical Society of Korea
• /
• v.11 no.1
• /
• pp.44-48
• /
• 2007

A two-stage gain-clamped erbium doped fiber amplifier (GC-EDFA) using a pump laser diode and a 16 channel wavelength division multiplexing (WDM) with 0.8 nm spacing in C band of $1,545{\sim}1,560nm$ wavelength is experimentally demonstrated for a burst packet mode optical switching system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.7
• /
• pp.1777-1784
• /
• 1998

The packet error rates of an optical packet switching node with an optical address processor using an EDFA in order to detect M-ary correlation pulses at a fiber-optical delay line matched filter output have been evaluated. Effects of A PIN diode NEP, the gain and noise figure of the EDFA, and the bandwidth of an optical filter on the packet error rate of the switching node have been compared. There is negligible error rate change depending upon the variation of the PIN diode NEP and the EDFA gain. If the bandwidth of the optical filter is below 10 times of the data rate, there is no appreciable effect on the error rate. If the noise figure of the EDFA increases, however, the power penalty increases as much as the noise figure increment at all the bit rates and for address code sets considered in this work.

• ETRI Journal
• /
• v.39 no.4
• /
• pp.525-534
• /
• 2017

A hardware-acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software-defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network-intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA-10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.11C
• /
• pp.123-132
• /
• 2001

This paper proposes a sound multicast packet-switching method which can less affect QoS(Quality of Service) degradation. The method includes a switch fabric with extra switching paths dedicated f()r multicast packets. Presented also are both a buffering structure and a scheduling algorithm for the proposed method. Simulation analysis for the method shows that the switching delay of unicast packets is decreased even though arrival rate of multicast packets is increased.

• Journal of the Korea Society of Computer and Information
• /
• v.21 no.6
• /
• pp.47-53
• /
• 2016

This paper deals with the capacity constrained time slot assignment problem(CTSAP) that a satellite switches to traffic between $m{\times}n$ ground stations using on-board $k{\leq}_{min}\{m,n\}$ k-transponders switching modes in SS/TDMA time-division technology. There was no polynomial time algorithm to solve the optimal solution thus this problem classified by NP-hard. This paper suggests a heuristic algorithm with O(mn) time complexity to solve the optimal solution for this problem. Firstly, the proposed algorithm selects maximum packet lengths of $\({mn \atop c}\)$ combination and transmits the cut of minimum packet length in each switching mode(MSMC). In the case of last switching mode with inefficient transmission, we applies a compensation strategy to obtain the minimum number of switching modes and the minimum makespan. The proposed algorithm finds optimal solution in polynomial time for all of the experimental data.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.3 no.4
• /
• pp.274-279
• /
• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.