• 대한전자공학회논문지
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• 제22권6호
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• pp.114-123
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• 1985

이 논문은 packet switching 방식에 의한 공중 computer 통신망 개발에 관한 4편의 논문중 제 2부의 논문으로 제 1부의 KORNET의 개요 및 netwo.k managementcenter (NMC)개발에관한 논문에 이어 KO-RNET의 설계와 networhnode Processor(NNP)의 개발에 대해 기술한다. KORNET은 3개의 NNP와 하나의 NMC 로 일차 구성하였는데, NNP는 MC68000 microprocessor를 이용한 multiprocessor system으로 구현되었고, HMC는 중형 computer인 Mv/8000 system을 사용하여 개발하였다. KORNET에서의 packet service 방식은 virtual circuit(VC) 방식으로 하고 routing은 node나 선로의 상태변화에 쉽게 대처할 수 있는 분산적응방식(distributed adaptive routinB)을 사용하였다. 또한, buffo. management는 dy-namic sharing 방식을 채택하여 storage의 사용에 대한 효율성을 높였다. NNP system의 hardware는 modularity를 고려하여 확장이 용이하게 하였으며, software는 CCITT 권고사항 X.25, X.3, X.28, X.29등을 따라 구현하였다.

• 정보와 통신
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• 제19권9호
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• pp.77-85
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• 2002

In this paper, we introduce an ADSRC(hdvanced DSRC) OFDM packet communication system which has been developed by ETRI. The ADSRC system is targeted to provide high terminal mobility, high data rate and seamless service in roadside environment for mobile office services. We discuss the requirements of the ADSRC communication system for mobile office services, and the system design specification to meet them with regard to air interface. The ADSRC packet communication systems consist of the MAC processor block, the OFDM packet modem block and the RF block. The MAC processor block handles medium access control and the test. The OFDM packet modem transmits data packets at up to 24Mbps adaptively and recovers the data from RF block. We describe the ADSRC packet communication system architecture and the ADSRC system protocol.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.23-26
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• 2002

In this paper, we modelize several scheduling algorithms for real-time packet filtering tasks based on the multi-threaded multi-processor architecture for the network security system like the firewall and compare the performance of the algorithms by implementing the algorithms and doing a number of empirical tasks. As the matrices of the performance we use the idle factor and the packet transfer rate. We get the idle factors and the packet transfer rates according to the transfers of the packet sizes from 64 bytes to 1500 bytes.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.635-638
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• 2002

In this paper, the connection device of RS232C and TCP/IP implementation using ARM processor and LINUX is proposed. Data interaction flash memory the multiple serial ports are transferred to ARM processor and the data are processed and formed into data packet for transfer via internet protocol. Packet flash memory Internet is decoded to extract the serial port data. The serial ports supports RS232C asynchronous protocol communication and control program is developed in GNU-C and installed in the on-board memory for packet conversion and control. The research result can be applied to terminal server, printer server and multiple serial ports equipments.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2003년도 봄 학술발표논문집 Vol.30 No.1 (C)
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• pp.503-505
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• 2003

패킷망을 통해 음성, 영상, 데이터를 동시에 제공할 수 있는 차세대 네트워크(NGN) 개념이 제안되어 현재 네트워크 상에 전개되어 가고 있다. 하지만 NGN의 Softswitch의 구성을 위해서는 현재의 PSTN 내의 Class 4/5 switch를 NGN의 구성에 맞게 끔 Access Gateway 및 Media Gateway로 교체해 나가야 하며 교체 후에도 소비자의 새로운 서비스 신설 요구에 신속하게 부합하기 위하여 기존 시스템의 서비스 중단없이 새로운 서비스 및 신규 프로토콜을 신속히 전개할 수 있는 개념은 필수적인 요소가 되었다. 이러한 점을 지원하기 위하여 본 논문에서는 개방형 네트워크 아키텍처 접근 방식인 Active Network의 개념을 응용한 차세대네트워크 Media Gateway Controller내의 이산 메커니즘 적용 Active Packet Processor도입하였다.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2001년도 The Seoul International Simulation Conference
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• Journal of Communications and Networks
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• 제4권3호
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• pp.209-220
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• 2002

In this paper, we propose a hierarchical packet scheduling technique to closely approximate a hierarchical extension of the generalized processor sharing model, Hierarchical Generalized Processor Sharing (H-GPS). Our approach is to undertake the tasks of service guarantee and hierarchical link sharing in an independent manner so that each task best serves its own objective. The H-GPS model is decomposed into two separate service components: the guaranteed service component to consistently provide performance guarantees over the entire system, and the excess service component to fairly distribute spare bandwidth according to the hierarchical scheduling rule. For tight and harmonized integration of the two service components into a single packet scheduling algorithm, we introduce two novel concepts of distributed virtual time and service credit, and develop a packet version of H-GPS called Hierarchical Fair Queueing (HFQ). We demonstrate the layerindependent performance of the HFQ algorithm through simulation results.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• 한국정보시스템학회지:정보시스템연구
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• 제14권3호
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• pp.97-104
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• 2005

The paper proposes an implementation architecture of DiffServ-over-MPLS traffic engineering (TE) on Intel IXP2400 network processor using Intel IXA SDK 4.0 Framework. Program architecture and functions are described. Also fast and scalable range-match classification scheme is proposed for DiffServ-over-MPLS TE that has been integrated with functional blocks from Intel Microblocks library. Performance test shows that application can process packets at approximate data rate of 3.5 Gbps. The proposed implementation architecture of DiffServ-over-MPLS TE on Network processor can provide guaranteed QoS on high-speed next generation Internet, while being flexible and easily modifiable.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2012년도 추계학술발표대회
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• pp.42-45
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• 2012

A network processor (NP) is an application-specific instruction-set processor for fast and efficient packet processing. There are many issues in compiler's code generation and optimization due to NP's hardware constraints and special hardware support. In this paper, we describe in detail how to resolve the issues. Our compiler was developed on LLVM 3.0 and the NP target was our in-house network processor which consists of 32 64-bit RISC processors and supports multi-context with special hardware structures. Our compiler incurs only 9.36% code size overhead over hand-written code while satisfying QoS, and the generated code was tested on a real packet processing hardware, called S20 for code verification and performance evaluation.