• Title/Summary/Keyword: Package Effect

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Effect of Influencer's Social Media Number of Followers on Purchase Intention in the Travel Industry of Vietnam: The Moderating Role of Package Tour Price

  • Thi Hoai DANG;Thi-Tuyet TRAN;Cao Cuong HOANG
    • Journal of Distribution Science
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    • v.22 no.4
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    • pp.37-46
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    • 2024
  • Purpose: Social media influencers (SMIs) have become significant sources of information influencing their followers' purchase intentions; few studies have been published on the effect of the number of followers and package tour prices on followers' purchase intention within the Vietnam travel industry utilizing naïve theories. This study examined the relationship between the number of followers and purchase intention and tested the moderating role of package tour price. Research Design, data and methodology: A 2 (number of followers: high vs. medium) × 2 (package tour price: high vs. low) between-subjects factorial design was used. 395 Vietnamese students (114 men, 281 women; Mage = 19.99, SDage = 1.25) from Thuongmai University participated in the study. ANOVA and PROCESS MARCO were used to test hypotheses. Results: Findings indicate that participants show a higher purchase intention for SMIs with a higher number of followers than those with a medium one. When the package tour price is high, participants with a medium number of followers show a greater purchase intention than those with a high one. Conclusion: This recommendsthat tourism managers collaborate with SMIs with a high number of followers when the package tour price is low and with SMIs with medium ones when the package tour price is high.

Effect of Underfill on $\mu$BGA Reliability ($\mu$BGA 장기신뢰성에 미치는 언더필영향)

  • 고영욱;신영의;김종민
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.05a
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    • pp.138-141
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    • 2002
  • There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

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Post Silicon Management of On-Package Variation Induced 3D Clock Skew

  • Kim, Tak-Yung;Kim, Tae-Whan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.139-149
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    • 2012
  • A 3D stacked IC is made by multiple dies (possibly) with heterogeneous process technologies. Therefore, die-to-die variation in 2D chips renders on-package variation (OPV) in a 3D chip. In spite of the different variation effect in 3D chips, generally, 3D die stacking can produce high yield due to the smaller individual die area and the averaging effect of variation on data path. However, 3D clock network can experience unintended huge clock skew due to the different clock propagation routes on multiple stacked dies. In this paper, we analyze the on-package variation effect on 3D clock networks and show the necessity of a post silicon management method such as body biasing technique for the OPV induced 3D clock skew control in 3D stacked IC designs. Then, we present a parametric yield improvement method to mitigate the OPV induced 3D clock skew.

Study on Vibration and Thermal Characteristics Applying Staking to CCGA Package for Space Applications (우주용 CCGA에서 Staking 적용에 따른 진동 및 열 특성 연구)

  • Jeong, Myung Deuk;Jung, Sunghoon;Hong, Young Min
    • Journal of the Korea Institute of Military Science and Technology
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    • v.23 no.6
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    • pp.574-581
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    • 2020
  • This paper describes the stacking effect for Ceramic Column Grid Array(CCGA) packages used for satellites. Reflow Soldering Process suitable for CCGA package with back structure was set as the process development goal to meet European Cooperation for Space Standardization(ECSS) standard. After analyzing the stacking effect according to the type of CCGA, it is verified by applying it to the CCGA Reflow Soldering Process. In order to confirm the validity of the staking effect analyzed in terms of vibration and thermal characteristics, it is verified through actual specimen production. It analyzes the cause of crack occurrence in the CCGA package and estimates the crack generation point using previously acquired inspection data.

Estimate on related to Chip Set and the other Various Parameter in Electronic Plastic Package (반도체 패키지의 칩셋과 다른 설계변수와의 연관성 평가)

  • Kwon, Yong-Su
    • Journal of the Korean Society of Industry Convergence
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    • v.2 no.2
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    • pp.131-137
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    • 1999
  • Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

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An Examples Development and Implementation of Core Skill-TLP Package in Patient Management (문제중심학습 개념의 환자관리 Core Skill-TLP 교육교재 개발 및 적용)

  • Lee, Young-Ah
    • The Korean Journal of Emergency Medical Services
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    • v.14 no.2
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    • pp.25-40
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    • 2010
  • Purpose : The purpose of this study was to develop and apply a Core Skill-TLP(Core Skill-Tutorial, Laboratory, Practicum) package in Patient Management and to effect of core skill-TLP education. Methods : This study was used to developed Patient Management' Core Skill-TLP package throughout 14 steps of Core Skill-TLP package development model. Then, Core Skill-TLP Learning methodology was implemented in first year student in the undergraduate emergency medical technology, and survey was done. Results : 1. Core Skill-TLP package model was presented based on conceptual model of PBL(S-PBL). 2, The student in OSCE did significantly better in clinical patient management core skills performance. 3. As to the satisfaction of Core Skill-TLP package management, student, tutor and self-satisfaction score was 3.21, 3.42, 3.38 respectively. Conclusion : This study was suggested that Core Skill-TLP education would be necessary with well-structured package and achieved advantage of simulation and PBL.

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Visco-Elastic Fracture Analysis of IC Package under Thermal Loading (열하중하에 있는 IC 패키지의 점탄성 파괴해석)

  • 이강용;양지혁
    • Journal of the Korean Society for Precision Engineering
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    • v.15 no.1
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    • pp.43-50
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    • 1998
  • The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

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Integrated Circuit(IC) Package Analysis, Modeling, and Design for Resonance Reduction (공진현상 감소를 위한 집적회로 패키지 설계 및 모델링)

  • 안덕근;어영선;심종인
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.133-136
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    • 2001
  • A new package design method to reduce resonance effect due to an IC package is represented. Frequency-variant circuit model of the power/ground plane was developed to accurately reflect the resonance. The circuit model is benchmarked with a full wave simulation, thereby verifying its accuracy. Then it was shown that the proposed technique can efficiently reduce the resonance due to the IC package.

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