• The Transactions of the Korean Institute of Power Electronics
• /
• v.9 no.5
• /
• pp.507-515
• /
• 2004

With the advent of fast power devices, the high dv/dt voltage produced by PWM inverts have been found to cause EMI noise, shaft voltage and bearing current. This paper describes the application of newly developed Conducted EMI reduction SVPWM technique in induction motor drives. The newly developed common mode voltage reduction SVPWM technique don't use any zero-vector states for inverter control, hence it can restrict the common mode voltage more than conventional PWM technique. The validity of the proposed technique by software approach is verified through simulation and experimental results.

• Journal of Power Electronics
• /
• v.16 no.6
• /
• pp.2024-2034
• /
• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• Proceedings of the KIPE Conference
• /
• 2001.07a
• /
• pp.151-154
• /
• 2001

This paper propose a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI. The new active common mode voltage damper is consisted of a half-bridge inverter and a common mode transformer with a blocking capacitor. Principle of the active common mode damper is as follow; by applying the compensation voltage which has the same amplitude and opposite polarity to the PWM inverter system. So, common mode voltage and high frequency leakage current can be reduced. Simulated and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• Journal of IKEEE
• /
• v.14 no.2
• /
• pp.1-8
• /
• 2010

In this paper, Green Mode Power IC is designed to reduce the standby power. The proposed and designed IC works for the Switch Mode Power Supply(SMPS) and has the function of PWM. To reduce the unnecessary electric power, burst mode and skip mode section are introduced and controlled by external power MOSFET to diminish the standby power. The proposed IC is designed and simulated by KEC 30V-High Voltage 0.5um CMOS Process. The structure of proposed IC is composed of voltage regulator circuit, voltage reference circuit, UVLO(Under Voltage Lock out) circuit, Ibias circuit, green circuit, PWM circuit, OSC circuit, protection circuit, control circuit, and level & driver circuit. Measuring the current consumption of each block from the simulation results, 1.2942 mA of the summing consumption current from each block is calculated and ot proved that it is within the our design target of 1.3 mA. The current consumption of the proposed IC in this paper is less than a half of conventional ICs, and power consumption is reduced to the extent of 1W in standby mode. From the above results, we know that efficiency of proposed IC is superior to the previous IC.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
• /
• v.15 no.7
• /
• pp.551-556
• /
• 2003

The present study concerns an experiment on the heating characteristics of a system air-conditioner (A/C) using PWM method or inverter method at low temperature con-ditions. The compressors used are digital scroll type and BLDC inverter type. Under the low outside temperature condition, -5$^{\circ}C$, -1$0^{\circ}C$, -15$^{\circ}C$, heating capacities and COPs are mea-sured by the psychometric calorimeter using air enthalpy method. Also, outlet air temperatures at heating operation mode are measured at -5$^{\circ}C$, -1$0^{\circ}C$ and -15$^{\circ}C$. Experimental results show that COPs of the system A/C using a PWM method are more effective than those of the inverter method at heating operation mode. Although the heater is on, COPs of PWM method are similar to those of BLDC inverter method. Moreover, the heating capacities of PWM method at -5$^{\circ}C$, -1$0^{\circ}C$ and -15$^{\circ}C$ are larger about 10~20% and outlet air tempe-rature at -15$^{\circ}C$ is larger about 10%, compared to the inverter method.

• Journal of Power Electronics
• /
• v.15 no.2
• /
• pp.504-517
• /
• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• Proceedings of the KIPE Conference
• /
• 1998.11a
• /
• pp.64-67
• /
• 1998

This paper proposes the hybrid PWM scheme that can obtain less harmonic characteristics in GTO inverters. By employing the variable of the dc-link voltage Vdc, the hybrid PWM pattern can ideally compensate the dc input fluctuation together with selected harmonics elimination. The transient behavior, which the magnetic flux and torque are altered and the large current flows instantly, may be produced when the mode change. To reduce such an undesirable transient behavior, it is also presented the technique for the gear changing of inverter operated with the hybrid PWM. The results are verified by simulations and experiments.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 1999.11a
• /
• pp.157-161
• /
• 1999

This paper presents a Single-phase Semi-Bridge PWM Converter, which features Continuos Conduction Mode and Phase-adjusted Unipolar PWM Method. The reduced conduction losses are achieved by the employment of a single converter, instead of the typical configuration composed of a front end rectifier followed by a boost converter. Theoretical principle of operation, a design example and Simulation results of a 3kW Semi-Bridge PWM converter with 220 Vrms input voltage and 400 Vdc output voltage are presented.

• Journal of IKEEE
• /
• v.14 no.2
• /
• pp.90-97
• /
• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 2002.11a
• /
• pp.151-156
• /
• 2002

The output voltage of Synchronous Generator is regulated constantly by field current control in excitation system. A synchronous generator is equipped with an automatic voltage regulator(AVR), which is responsible for keeping the constant output voltage under normal operating conditions about various levels. High frequency PWM converter (Current Mode Control Buck converter) type excitation system for synchronous generator is able to sustain output voltage level properly when the fault condition happened. This paper deals with the design and evaluation of the excitation system controller for a synchronous generator to improve the steady state and transient stability. The simulation and experimental results show that the proposed excitation system is improve the respons time by the AVR(automatic voltage regulator) of 50kW synchronous generator that is applied the current mode control excitation system.