• Journal of Power Electronics
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• v.15 no.6
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• pp.1524-1532
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• 2015

Conventional space vector pulse width modulation based asymmetrical dual inverter configuration produces high common mode voltage (CMV) variations. This CMV causes the flow of common mode current, which adversely affects the motor bearings and electromagnetic interference of nearby electronic systems. In this study, a simple and generalized carrier based pulse width modulation (PWM) technique is proposed for dual inverter configuration. This simple approach generates various continuous and discontinuous modulating signals based PWM algorithms. With the application of the discontinuous modulating signal based PWM algorithm to the asymmetrical dual inverter configuration, the CMV can be reduced with a slightly improved quality of output voltage. The performance of the continuous and discontinuous modulating signals based PWM algorithms is explored through both theoretical and experimental studies. Results show that the discontinuous modulating signal based PWM algorithm efficiently reduces the CMV and switching losses.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.12
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• pp.739-750
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• 2004

In case while M(modulation index) is more than 0.7, the spectrum of motor voltage and current of a conventional two-phase SRP-PWM scheme are not reduced considerably. To solve the problems of a conventional two-phase SRP-PWM, this paper proposes a two-phase SRP-PWM(DZSRP-PWM) with double zero vector mode which zero vector is selected as V(111) in case of M >0.7, and zero vector is selected as V(000) if M < 0.7. For the validity of the proposed method, the PSIM simulations and experiments were achieved. And the simulation and experiment results show that the voltage and current harmonics all over the modulation index are spread to a wide band area.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.777-780
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• 2003

In this paper, an improved full wave mode ZVT-PWM DC-DC Converter is presented to maximize the regeneration ratio of resonant energy by only putting an additional diode in series with auxiliary switch. The operation of auxiliary switch in a half wave mode makes possible the soft switching condition of all switches. Furthermore, the increase of the regeneration ratio to resonant energy results in low conduction losses and minimum voltage and current stresses. The operation principles of the proposed converters are analyzed using the PWM boost converter topology as an example. Theoretically analysis and experimental results verify the validity of the boost converter topology with the proposed full wave mode ZVT-PWM converters

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1882-1885
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• 1998

This paper proposes the advanced PWM method which can reduce common-mode voltage in 3 phase PWM converter/inverter system. By shifting the zero voltage vector of inverter in a sampling period, it is possible to cancel out a common-mode voltage pulse defined by switching functions of converter and inverter. Without any loss of control performance of converter/inverter system, overall common-mode voltage can be reduced by one-third compared with that of conventional PWM scheme.

• Transactions on Control, Automation and Systems Engineering
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• v.3 no.4
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• pp.257-261
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• 2001

Nonlinear pulse width modulation (PWM) controlled system is considered to achieve control performance of thruster controlled spacecraft. The actual PWM controlled motions occur, very closely, around the average model trajectory. Furthermore nonlinear PWM controller design can be directly applied to thruster controlled spacecraft to determine thruster on-time. Sliding mode control for attitude tracking of three-axis thruster-controlled spacecraft is presented. Simulation results are shown which use modified Rodrigues parameters and sliding mode control law to achieve attitude tracking of a three-axis spacecraft with thrusters.

• Journal of Power Electronics
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• v.19 no.4
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• pp.907-921
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• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.5
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• pp.443-450
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• 2000

A PWM inverter for an induction motor often has a problem with a high frequency leakage current that flows through stray capacitors between stator windings and a motor frame to ground. This paper proposes a new type of Active Common Mode Voltage Canceler circuit for the reduction of common mode voltage and high frequency leakage current generated by the PWM VSI-fed induction motor drives. The compensating voltage applied by the common made voltage canceler has the same amplitude as, hut the opposite polarity to, the common mode voltage by PWM Inverter. Therefore, common mode voltage and high frequency leakage current can be canceled. The proposed circuit consists of four-level half-bridge inverter and common-mode transformer. Simulated and experimental results show that common mode voltage canceler makes significant contributions to reducing a high frequency leakage current.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.3
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• pp.133-139
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• 2002

In this paper, a prototype of an active auxiliary quasi-resonant DC link (QRDCL) snubber assisted voltage source bidirectional power converter (AC to DC and DC to AC) operating at zero voltage soft-switching (BVS) PWM nlode is presented for a Battery Energy Storage System (BESS). The operating principle of this QRDCL circuit and multifunctional control-based converter system, including PWM inverter mode in which energy flows from the battery bank to the three-phase utility-grid in addition to an active PWM converter mode in which energy flows from the utility-grid to the battery banks are described respectively by the control implementation on the basis of d-q coordinate plane transformation. The multifunctional operation characteristics of this three-phase ZVS PWM bi-directional converter with QRDCL is demonstrated fer a BESS under the power conditioning and processing schemes of energy supply mode and energy storage mode, and compared with a conventional three-phase hard switching PWM bi-directional converter for a BESS. The effectiveness of the three-phase ZVS PWM hi-directional converter with QRDCL is proven via the simulation analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.404-407
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• 2011

This paper presents a design of current mode PWM/PFM DC-DC Boost converter. This DC-DC Boost Converter operates with PWM mode at the heavy loads and with PFM mode at light loads. The DC-DC boost converter is designed with CMOS 0.35${\mu}m$ technology. It operates at 500KHz and can drive a load current up to 600mA. It has a maximum power efficiency of 92.1%. The total chip area is $1300{\mu}m{\times}1070{\mu}m$ including pads. The DC-DC boost converter operates in a wide range of load currents while occupying a small chip area.