• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.602-605
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• 2003

분산전원용 계통연계 인버터가 효율적인 분산전원으로 사용되기 위해서는 기존 계통과 협조 운전이 필요하다. 따라서 전류제어 외에 무효전력의 제어, 계통과 연계시의 PLL 제어, 단독운전 방지 제어 등의 다양한 기능이 필요하다. 그러나 단상 시스템의 경우, 3상 시스템과 달리 교류전력을 다뤄야 하므로, 제어 시 위상 지연이 발생하게 되고 무효전력을 제어하기 어려운 문제점등이 발생된다 따라서 본 논문에서는 이러한 문제점을 해결하기 위해 dq 모델을 단상시스템에 적용하여 단상 제어의 문제점을 보완하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.401-401
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• 2009

Recently, demands for the development of compact, lightweight power supplies with higher power density and higher efficiency have been increased. Since Piezoelectric Transformer (PT) was emerged in device and material industry, it has been suggested as a viable alternative to the magnetic transformer in some applications. PT has some advantages such as low profile and mechanical energy transfer with little electromagnetic interface (EMI). Also, PT can provide high voltage stepping ratio with good isolation and requires no copper windings saving copper usage especially for large voltage conversion differences. Conventional control of PT converter has mainly two-way. One is the pulse frequency modulation (PFM) control method and the other is the pulse width modulation (PWM) control with frequency fixed method. It is known that the maximum PT efficiency can be obtained when it operates near the resonant frequency of the PT. And, also PT's resonant frequency moves according to the load condition. Therefore, selection of PT converter control method is very difficult. This paper analyzes general piezo-electric converter modeling and proposes a guide-line to selection of control method and stabilization control.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.1-9
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• 1996

In the following paper, new architectural algorithm of clock and data recovery circuit is proposed for 622.08 Mbps optical communication receiver. New algorithm makes use of charge pump PLL using voltage controlled ring oscillator and extracts 8-channel 77.76 MHz clock signals, which are delayed by i/8 (i=1,2, ...8), to convert and recover 8-channel parallel data from 662.08 Mbps MRZ serial data. This circuit includes clock genration block to produce clock signals continuously even if input data doesn't exist. And synchronization of data and clock is doen by the method which compares 1/2 bit delayed onput data and decided dta by extracted clock signals. Thus, we can stabilize frequency and phase of clock signal even if input data is distorted or doesn't exist and simplify receiver architecture compared to traditional receiver's. Also it is possible ot realize clock extraction, data decision and conversion simulataneously. Verification of this algorithm is executed by DESIGN CENTER (version 6.1) using test models which are modelized by analog behavior modeling and digital circuit model, modified to process input frequency sufficiently, in SPICE.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.25-31
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• 2017

This paper presents a 270/540/750/1500-Mb/s serial-data transmitter realized in a $0.13-{\mu}m$ CMOS technology for the applications of video data transmission. A low-cost RG-58 copper cable(5C-HFBT-RG6T) is exploited as a transmission medium connected to a single BNC connector, which shows cable loss 45 dB in maximum at 1.5 GHz. RLGC modeling provides an equivalent circuit for SPICE simulations of which characteristics are very similar to the measured cable loss. The loss can be compensated by pre-emphasis at transmitter and equalization at receiver if needed. Measurements of the proposed transmitter chip demonstrate the operations of 270-Mb/s, 540-Mb/s, 750-Mb/s and 1.5-Gb/s, and provide the output voltage levels of $370mV_{pp}$ at 1.5 Gb/s even with the pre-emphasis turned-off. The total power consumption is 104 mW from 1.2/3.3-V supplies and the chip occupies the area of $1.65{\times}0.9mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.777-786
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• 2003

The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of frequency synthesizer. To accurately model the phase noise contribution of noise sources in frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of phase-locked loop. To evaluate the phase noise prediction model, the frequency synthesizers were fabricated and were evaluated by measured data and prediction data.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.397-409
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• 2007

Owing to needs of biomechanical comprehension and analysis to obtain various medical treatment designs which are related with the spine in order to cure and diagnose LBP patients, the FE modeling and nonlinear analysis of lumbosacrum including a partial ilium and iliolumbar ligaments, were carried out. First, we investigated whether the geometrical configuration of vertebrae displayed by DICOM slice files is regular and normal condition. After constructing spinal vertebrae including a partial ilium, a sacrum and five lumbars (from L1 to L5)with anatomical shape reconstructed using softwares such as image modeler and CAD modeler, we added iliolumbar ligaments, lumbar ligaments, discs and facet joints, etc.. And also, we assigned material property and discretized the model using proper finite element types, thus it was completely modeled through the above procedure. For the verification of each segment, average sagittal ROM, average coronal ROM and average transversal ROM under various loading conditions(${\pm}10Nm$), average vertical displacement under compression(400N), ALL(Anterior Longitudinal Ligament) and PLL(Posterior Longitudinal Ligament) force at L12 level, strains of seven ligaments on sagittal plane at L45 level and maximal strain of disc fibers according to various loading conditions at L45 level, etc., they were compared with experimental results. For the verification of multilevel-lumbosacrum spine including partial ilium and iliolumbar ligaments, the cases with and without iliolumbar ligaments were compared with ROM of experiment. The results were obtained from analysis of the verified FE model as follows: I) Iliolumbar ligaments played a stabilizing role as mainly posterior iliolumbar ligaments under flexion and as both posterior and anterior iliolumbar ligaments of one side under lateral bending. 2) The iliolumbar ligaments decreased total ROM of 1-8% in total model according to various motion conditions, which changed facet contact forces of L5S level by approximately 0.8-1.4 times and disc forces of L5S level by approximately 0.8-1.5 times more than casewithout ilioligaments, under various loading conditions. 3) The force of lower discs such as L45 and L5S was bigger than upper discs under flexion, left and right bending and left and right twisting, except extension. 4) It was predicted that strains of posterior ligaments among iliolumbar ligaments would produce the maximum 16% under flexion and the maximum 10% under twisting. 5) It's expected that this present model applies to the development and design of artificial disc, since it was comparatively in agreement with the experimental datum.