• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.888-894
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• 1986

In this paper, a phase locked loop control system is designed to have high performance and stability in a 2-phase bifilar winding PM step motor. The BODE diagram analysis method is used to improve the stability and dynamic characteristic of the closed loop control system. Also, a PLL servo is used to accomplish high-precision speed and to attain smooth ness. In applying the PLL control to the step motor, a new design method is suggested to solve the control problem which occurs as a result of the limited maximum acceleration of the step motor. A simple design method is suggested without using the complicated multi-step characteirstic of the step motor in constant voltage driving. Computer simulation results agree clorelg with experiments, indicating that the PLL servo system of the step motor designed is very useful.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.5
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• pp.775-784
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• 2010

In this paper we propose a design method of X band frequency hopping synthesizer in terms of phase noise and settling time with DDS driven PLL architecture, which has the advantages of high frequency resolution, fast settling time and small size. In addition, a noble method is proposed to remove the synthesizer output spurious signals due to superposition effect of DDS. The spurious signal which depend on its normalized frequency of DDS, can be dominant if they occur within the PLL loop bandwidth. We verify that the sources of that spurious signals are quasi-amplitude modulation and superposition effect, and suggest that such signals can be eliminated by intentionally creating frequency errors in the developed synthesizer.

• Journal of Power Electronics
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• v.18 no.1
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• pp.212-224
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• 2018

For maintaining a reliable and secure power system, this paper describes the design and implement of a single-phase grid-connected inverter with an enhanced phase-locked loop (PLL) and excellent power control performance. For designing the enhanced PLL and power regulator, a full-bridge voltage-controlled inverter (VCI) is investigated. When the grid frequency deviates from its reference values, the output frequency of the VCI is unstable with an oscillation of 2 doubling harmonics. The reason for this oscillation is analyzed mathematically. This oscillation leads to an injection of harmonics into the grid and even causes an output active power oscillation of the VCI. For eliminating the oscillation caused by a PLL, an oscillation compensation method is proposed. With the proposed method, the VCI maintains the original PLL control characteristics and improves the PLL robustness under grid frequency deviations. On the basis of the above analysis, a power regulator with the primary frequency and voltage modulation characteristics is analyzed and designed. Meanwhile, a small-signal model of the power loops is established to determine the control parameters. The VCI can accurately output target power and has primary frequency and voltage modulation characteristics that can provide active and reactive power compensation to the grid. Finally, simulation and experimental results are given to verify the idea.

• Journal of IKEEE
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• v.12 no.2
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• pp.81-86
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• 2008

In wireless communication system using 2.4GHz radio link, data rate varies with time due to interferences, which causes the performance degradation. Therefore, effective transmission methods are required to obtain better performance according to varying data rate. This paper proposes a novel method that increases the data rate, as well as the influence of different loop-filter bandwidths on the performance of the PLL. Experimental results show that the proposed method is effective because it can achieve higher throughput in various data rate.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.45-53
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• 1996

In this paper, the convergence behavior of timing phase when an adaptive partial response equalizer and decision-directed type of a PLL work together in a digital recording channel is described. The phenomena of getting biased in timing phase when the convergence parameter of an adaptive partial response equalizer and timing recovery constant of a PLL are not selected properly is introduced. The phenomena, occurring due to perturbation of timing phase, are analyzed, by computer simulation and the region of ocnvergence for timing phase is discussed. Also, a method to overcome the phenomena using a variable step-size parameter is described.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.54-62
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• 1988

For code division multiple access, a frequency synthesizer of elementary components is necessary in the system application of frequency hopped spread spectrum communication. This paper proposes the model of N-loop PLL frequency synthesizer to be adaptied for generating the output frequency resultes in the frequency hopping pattern and to be easy in practical application of the system. It was analyzed how the frequency divider ratio distribute, what the method to decide frequency divider ratio is and what relationship of bandwidth of BPF and degree of multiple have is also analyzed in order to hop the desired frequency output.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.219-220
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• 2014

기존의 SRF-PLL방법은 구현이 간단하고 정상전원에서 위상각 추정 성능이 우수하지만 불평형 전원하에서 위상각 추정 성능이 저하된다. 본논문에서는 상간전압의 위상변화, 상전압의 크기변동 및 오프셋이 발생된 불평형 전원하에서 변동된 값들을 실시간으로 보상하여 위상각을 검출하는 재귀형 최소 자승법을 이용한 SRF-PLL방법을 제안한다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.526-527
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• 2015

본 논문은 계통에 전력을 변동하여 계통 임피던스를 추정하는 기법의 문제점을 분석하고 개선된 역상분 전류 주입을 이용한 임피던스 추정 기법을 제안한다. 기존의 계통 임피던스 추정 기법에서는 유, 무효 전력의 크기를 변화시키고, 그에 따른 두동작점에서 측정된 전압의 변동량을 통해 계통 임피던스를 계산한다. 하지만 일반적인 계통 연계형 인버터에는 전원 전압의 위상을 추종하는 PLL이 동작하고 있으며, 이 PLL은 정상 상태에서 얻을 수 있는 전류 주입에 따라 발생하는 d-q축 전압의 변동량을 왜곡시켜 추정 오차를 유발한다. 따라서 본 논문에서는 불평형 전원을 독립적으로 제어하는 듀얼 제어기와 정상분 PLL 기법을 사용하여 역상분 전류에 의한 역상분전압의 변동량만으로 PLL에 의한 PCC 전압의 정상 상태 측정 오차를 제거하여 계통 임피던스를 정확히 추정하는 기법을 제안한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.35-40
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• 2012

In DC-DC converters, a PWM/PFM dual mode control method is commonly used to maintain a high efficiency over a wide range of load variation. Since the control mode is selected according to the load condition, the chip area is increased due to additional circuit for mode control and the optimum efficiency cannot be achieved around the mode transition point. To solve such problems, a new integrated control method is proposed in this paper, in which a PLL is used in the current mode PWM control circuit instead of an oscillator. The proposed integrated control method is verified through a design of a buck converter using PSIM simulation. Simulation of the complete buck converter circuit by Cadence Spectre showed a maximum efficiency of 94.7% at a load current of 250mA and an efficiency of 85.4% at a load current of 10mA under the light load condition.