• Journal of Power Electronics
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• v.16 no.4
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• pp.1375-1386
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• 2016

To decouple the secondary saliencies in sensorless permanent magnet synchronous machine (PMSM) drives, a repetitive control (RC) in the angle domain is proposed. In this paper, the inductance model of a concentrated windings surface-mounted PMSM (cwSPMSM) with strong secondary saliencies is developed. Due to the secondary saliencies, the estimated position contains harmonic disturbances that are periodic relative to the angular position. Through a transformation from the time domain to the angle domain, these varying frequency disturbances can be treated as constant periodic disturbances. The proposed angle-domain RC is plugged into an existing phase-locked loop (PLL) and utilizes the error of the PLL to generate signals to suppress these periodic disturbances. A stability analysis and parameter design guidelines of the RC are addressed in detail. Finally, the proposed method is carried out on a cwSPMSM drive test-bench. The effectiveness and accuracy are verified by experimental results.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.665-669
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• 2004

Generally, Slotless PM BLDC drive system is necessary that the three Hall-ICs evenly be distributed around the stator circumference and encoder be installed in case of the 3 phase motor. So, the Hall-ICs are set up in this motor to detect the main flux from the rotor, and the output signal from Hall-ICs is used to drive a power transistor to control the winding current. However, instead of using three Hall-ICs and encoder, we used only two Hall-ICs for the permanent magnet rotor position and for the speed feedback signals, and also for a microcontroller of 16-bit type (80C196KC) with the 3 phase Slotless PM BLDC whose six stator and two rotor designed. Two Hall-IC Hc and $H_B$ are placed on the endplate at 120 degree intervals, and with these elements, we can estimate information of the others phase in sequence through a rotating rotor.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.77-84
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• 2000

In this paper, we discuss a symbol clock extraction scheme based on maximizing the band-edge component of the transmitted signal frequency spectrum for applications to 51.84Mbps VDSL system which uses a 16-QAM. The major characteristics of the digital PLL are examined. In addition, we suggest an efficient design method of a sinusoidal look-up table which is used for NCO.

• The Journal of the Korea Contents Association
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• v.7 no.3
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• pp.42-49
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• 2007

This paper implements RFID(radio-frequency identification)System to which the system was apply SS(Spread Spectrum) method. The system designed by using the algorithm for microprocessor with PLL of the receiver, PN spread, modulation and demodulation of the transceiver, and transistor amplifier for the output of stabilized BPSK (Binary Phase Shift Keying) signal. furthermore, it reduced the interference of the signal by designing the micro-strip narrow banded patch antenna, which is convenient for printing and producing, and decreased the volume of filter size in the system. It is also designed for the lower powered system with the possible application to UHF band of $860\sim930MHz$ for the international standard frequency band, which is the quota share of RFID distribution system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.267-273
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• 1998

In this paper, we designed a charge pump with a differential current switching structure and it was made of a MESFET with high speed switching Property compared with CMOSFETs. The charge pump with a differential current switching structure is analyzed about operating property of circuit in high frequency band. Also we propose a method on it's characteristics estimation. The designed circuit is simulated by HSPICE simulator, and in view of the results we think that the charge pump of this study can be used in circuits of 1 GHZ frequency band grade.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1709-1717
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• 2015

In remote islands PV (Photo Voltaic) panel with BESS (Battery Energy Storage System) supplies electric power to the customers in parallel operation with EG (Engine Generator) to save fuel consumption and to mitigate environmental load. BESS operates in voltage control mode when it supplies power to the load alone, while it operates in current control mode when it supplies power to the load in parallel with EG. This paper proposes a smooth mode change scheme from current control to voltage control of BESS by adding proper initial value to the integral part of voltage control, and a smooth mode change scheme from voltage control to current control by tracking the EG output voltage to the BESS output voltage using PLL (Phase-Locked Loop). The feasibility of proposed schemes was verified through computer simulations with PSCAD/EMTDC, and the feasibility of actual hardware system was verified by experiments with scaled prototype. It was confirmed that the proposed schemes offer a seamless operation in the stand-alone power system in remote islands.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.523-524
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• 2016

본 논문에서는 자기저항 (Magnetic Resistive, MR)각도 센서에서 자속 간섭 및 축 진동과 같은 외란에 의해 발생하는 각도맥동을 해결하는 방법이 연구되었다. 외란에 의한 각도 맥동은 일정한 기계각 속도 한 주기 내에서 전기각 속도가 불균일하게 측정되는 현상이다. 이를 해결하기 위해 위상동기루프 (phase locked loop, PLL)를 적용하였고, 자기저항 각도 센서의 각도 맥동을 효과적으로 제거하였다.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.188-190
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• 2009

본 연구에서는 독립운전 검출기법의 능동적 기법 중 AFDPF 기법을 IEEE Std 929-2000에 제시된 독립운전 시험 조건하에서 위상동기기법 영점검출방식(Zero Crossing PLL)을 적용하여 독립운전 시 chopping fraction에 따른 PCC(Point of Common Coupling)의 주파수 변동 특성을 PSIM을 통하여 분석하였다

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.171-172
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• 2017

본 논문에서는 분산전원의 계통 연계형 시스템에서의 단독운전 검출 방식인 RPV(Reactive Power Variation)기법에 대한 고찰과 주파수 검출 방식을 분석한다. IEEE 929 - 2000에 근거하여 RPV 기법에서의 NDZ에 대하여 살펴보고, PLL(Phase Locked Loop) 기법을 이용한 주파수 검출에 대한 분석 및 설계와 이를 통한 단독운전 검출을 하고자 한다. 시뮬레이션을 통하여 타당성을 검증하였다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.950-953
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• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.