• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.1-5
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• 2010

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.5
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• pp.466-476
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• 2011

In this paper, a high-performance current control for the single-phase PWM converter under distorted source voltages is proposed using a composite observer. By applying the composite observer, the fundamental and high-order harmonic components of the source voltage and current are extracted without a delay. The extracted fundamental component is used for a phase-lock loop (PLL) system to detect the phase angle of the source voltage. A multi-PR (proportional-resonant) controller is employed to regulate the single-phase line current. The high-order harmonic components of the line current are easily eliminated, resulting in the sinusoidal line current. The simulation and experimental results have verified the validity of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.10
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• pp.914-924
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• 1991

It has been generally used for PLL(Phase Locked Loop) to be synthesized randomly chosen frequency state, but the PLL locking time was inevitable element. A direct digital synthesizer. Which makes output frequency directly in sine wave by a phase accumulating method, could be leiminate the defect, although a phase distortion in frequency spectrum. In order to improve this disadvantage, the phase accumulating method is reconsidered in the side of he output wave formula expression. A new mechanism is proposed, and it is constructed by a most suitable logic elements. The spectrum of synthesized sine waveform is simulated and compared with a measured value, and it’s the coherence frequency hoppong state with the PN(Pseudo Noise) code sequence is confirmed. In this results, the power levels of phase distortion harmonics are decreased to 10~25dB and bandwidths are increased to 420kHz.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.31-39
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• 2012

In this paper, we propose a microprocessor-based automatic voltage regulator(AVR) to reduce consumers' electric energy consumption and to help controlling peak demanding power. Hybrid Switching Automatic Voltage Regulator (HS-AVR) consist of a toroidal core, several tap control switches, display and command control parts. The coil forms an autotransformer which has a serial main winding and four parallel auxiliary windings. It controls the output voltage by changing the combination of the coils and the switches. Relays are adopted as the link switches of the coils to minimize the loss. To make connecting and disconnecting time accurate, relays of the circuit have parallel TRIACs. A software phase locked loop(PLL) has been used to synchronize the timings of the switches to the voltage waveform. The software PLL informs the input voltage zero-crossing and positive/negative peak timing. The traditional voltage transformers and AVRs have a disadvantage of having a large mandatory capacity to accommodate maximum inrush current to avoid the switch contact damage. But we propose a suitable AVR for every purpose in smart grid with reduced size and increased efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.103-109
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• 2007

This paper presents behavioral models using SIMULINK and Verilog-a for a PLL based fractional-N frequency synthesizer. By adopting a top-down approach along with the traditional bottom-up transistor level design in parallel, the design time is greatly shortened, and a co-verification method for both the digital and the analog part is considered. Under this consideration, the SIMULINK modeling reduces simulation time and easily estimates the PLL's performance on the top level. Verilog-a is able to verify the feasibility of each blocks at first hand because it is compatible with transister level circuits. Then, an efficient way of the design is presented by comparing the results of both models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1326-1331
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• 2001

This paper has been studied about design of a transceiver for data transmission. The transceiver has bandwidth of 424.7~424.95 MHz and uses half duplex communication method, PLL synthesized, 20 channel, 12.5 KHz channel bandwidth and FSK modulation/demodulation method. The transmission set is designed using low noise amplifier and power amplifier Also, it consists of low pass filter and resonation circuit for decrease of spurious signal. The receiver set is designed using dual conversion method. Finally, the transceiver set achieves the following characteristics 9.71dbm output power, 47dbc spurious property and $\pm$12.3 Jitter at sensitivity of -1134dbm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.10
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• pp.1467-1472
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• 2014

This paper study on powering characteristic on speed variation of propulsion system of prototype 8200 electric locomotive propulsion system through simulation modeling. For this purpose, it being applied in the field of railway IGBT (Insulated Gate Bipolar Transistor) elements are used. Converter was performed PLL (Phase-Locked Loop) control method that is used to control the phase and output voltage, and the inverter was carried an indirect vector control method to control the speed of traction motor. The results of simulation by modeling and experimental unit, we was confirmed that converter is controlled a unity power factor and output voltage by reference voltage. Also traction motor was controlled by indirect vector control and SVPWM inverter switching method very well.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.1
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• pp.48-56
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• 2006

This paper studies particularly applicable method for sensorless PM BLDC motor drive system. The waveform of the motor internal voltages(or back emf) contains a fundamental and higher order frequency harmonics. Therefore the third harmonic component is extracted from the stator phase voltage. The resulting third harmonic signal keeps a constant phase relationship with the rotor flux for any motor speed and load condition. Also because of low resolution of estimated signal obtained by the proposed sensorless algorithm, to improve the wide range of speed response characteristic more exactly, we propose the rotor position signal synthesizer using PLL circuit based on estimated signals. Some experimental results are provided to demonstrate the validity of the proposed control method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.989-995
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• 2001

흔히 전송매체와 연결되는 물리계층에서는 수신된 데이터열에서 동기를 획득하는 과정이 필요하다. 기가비트 이더넷에서는 PMA에서 PCS로 데이터열을 전송할 때 62.5MHz 두 개의 클럭에 맞추어 교대로 보내는 절차를 표준안으로 채택하고 있기 때문에 수신된 데이터열을 처리하기 위한 125MHz 클럭을 생성해내는 PLL이 필요하다. 그러나 PLL은 구현하기가 어렵다. 다른 대안들로는 FIFO를 활용하는 방법과 62.5MHz 클럭을 이용한 이중 데이터열 처리 방법 등이 있다. FIFO를 이용한 방법에서는 오버플로우가 발생할 수 있으며, 이중 데이터열 처리 방법에서는 표준안과 다른 별도의 수신부 설계가 필요하다. 본 논문에서는 언급한 방법들을 사용하지 않으면서도 표준안을 따르며 비용 효과적인 하나의 방안으로 송신부 클럭에 수신된 데이터열을 재정렬 시킬 수 있는 DSM(Divide-Select-Merge) 방법을 제안한다.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1281-1283
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• 1995

In this paper, we develop a prototype of the Optical SCM transmission module. This module is possible to application to electric facilities for control and measurements. Transmission channel number is two channels, namely, image and digital signal. In the image transmission, modulation method is AM, baseband signal is NTSC video signal and demodulation use PLL. Modulation of digital signal is QPSK, 1.544Mbps and demodulation use PLL. First, we calculate theoretical analysis about RF and Optical link in the transmission. This calculation is well correspond with practical system and transmission experiment is excellent, but this is only two channel model. And now, we plan to multichannel transmission to measure intermodulation, frequency assignments and optimal channel numbers et al.