• Journal of Power Electronics
• /
• v.13 no.2
• /
• pp.322-328
• /
• 2013

This paper presents a modified Current Source Parallel Resonant Push-pull Inverter (CSPRPI) for single phase induction heating applications. One of the most important problems associated with current source parallel resonant inverters is achieving ZVS in transient intervals. This paper shows that a CSPRPI with the integral cycle control method has dynamic ZVS. According to this method, it is the Phase Locked Loop (PLL) circuit that tracks the switching frequency. The advantages of this technique are a higher efficiency, a smaller package size and a low EMI in comparison with similar topologies. Additionally, the proposed modification results in a low THD of the ac-line current. It has been measured as less than %2. To show the validity of the proposed method, a laboratory prototype is implemented with an operating frequency of 80 kHz and an output power of 400 W. The experimental results confirm the validity of the proposed single phase induction heating system.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.18 no.3
• /
• pp.205-210
• /
• 2013

This paper presents a novel hall sensor fault detection and fault-tolerant control method for a high-speed permanent magnet synchronous motor (PMSM) drive system. A phase locked loop (PLL) type position estimator is used with a conventional interpolation based rotor position estimator to reduce position errors due to misalignment of hall sensors. The expected trigger time of hall sensor's output is used for detecting hall sensor fault condition and the PLL type position estimator is reconfigured for fault-tolerant control at the hall sensor fault condition. The proposed method can minimize current ripples during the transition from sensored control using hall sensors to sensorless control. Experimental results have been proposed to prove the validity of the proposed method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.4
• /
• pp.653-660
• /
• 2001

In this paper, we designed 2303.15MHz frequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise generated in the designed system through introducing the noise-modeling method suggested by Lascari we analyzed a variation of phase noise as according as that of offset frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL. As a result, In case of txco we found the reduce rapidly along the offset frequency after passed through that phase-noise was -160dBc/Hz before passed through a loop at 10kHz offset frequency and -162.6705dBc/kHz after passed through the loop, -180dBc/Hz at 100kHz offset frequency and -560dBc/kHz after passed through the loop. We can notice that the variance of third-order system more occurs (or the variance of second-order system in connection with noise bandwidth and variance factor of second-order and third-order system.

• Journal of the Institute of Convergence Signal Processing
• /
• v.6 no.2
• /
• pp.95-99
• /
• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Proceedings of the IEEK Conference
• /
• 2003.07c
• /
• pp.2589-2592
• /
• 2003

In this paper, a robust mixed H$_2$/H$\_$$\infty$/ output feedback control method is applied to the design of loop filter for PLL carrier phase tracking. The proposed method successfully copes with large S-curve slope uncertainty and a significant decision delay in the closed-loop that may exist In modern receivers due to a convolutional decoder or an equalizer. The objective is to design an output feedback controller which minimizes the H$_2$performance while satisfying the H$\_$$\infty$/ performance to guarantee the gain margin and phase margin for linear time invariant(LTI) polytopic uncertain systems. LMIs based approach is given to solve this problem. We can verify the H$\_$$\infty$/ performance satisfaction and minimize the phase detector error through the simulation result.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.77-79
• /
• 2007

The phase angle of the utility voltage is used in current control of grid-tied fuel cell power converter. Therefore if the detection of phase angle is a problem, Current control is affected by the distorted phase angle. This paper presents a problem of synchronous reference frame PLL algorithm for single-phase systems and proposes compensated synchronous reference frame PLL algorithm. The proposed method helps power quality improvement of grid-tied fuel cell power converter under distorted utility conditions. Simulation and experimental results are presented to demonstrate the validity of the proposed method.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.15 no.3
• /
• pp.179-187
• /
• 2010

This paper proposes a new anti-islanding method for single-phase grid-connected photovoltaic (PV) systems using Goertzel algorithm. The proposed scheme is based on inducing increases or decreases of frequencies of load voltage and current that is in the form of existences or periodical variations of the reactive power components. The frequency detection is needed to apply this power variation method to the grid-connected power converter. The proposed method is able to get a fast detection for anti-islanding without the effect of harmonics and noises. The simulation and experiment results validate the effectiveness of the proposed method.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.4
• /
• pp.199-204
• /
• 2010

Recently, the transmission amount of information that each single person requires is growing by development of electron information communication technology. So in this paper we analysis the phase noise characteristics to obtain a most suitable of SNR performance request characteristic by BER on CATV transmission system that satisfy performance request DOCSIS 2.0 standard. Especially we get the parameter value of PLL that satisfy phase noise characteristic request standard using developed simulator. Presented method can be used to obtain a performance request standard connection performance request standard of high speed CATV transmission system in the future.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.20 no.1
• /
• pp.72-80
• /
• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.2
• /
• pp.333-339
• /
• 2012

Global flow of communication is a trend of high speed, digitalization, and high-capacity. Furthermore, spread spectrum method has been dominantly utilized to efficiently use the frequency which is the scarce resource. The PLL (Phase Lock Loop) which is a widely used frequency synthesizer in communication systems has few problems such as status interferences and hence, this study utilized the DDS (Direct Digital Synthesis) which is a digital device that can minimize the problems of PLL for the study on the performance evaluation of high speed frequency hopping system design. We designed a system that practices high speed frequency hopping and interprets improvement of error-rates and evaluated its performance.