• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.17-21
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• 2010

In this paper, we have introduced a new way to design low phase noise PLL which can apply to the Ultra wideband as meeting performance requirements based on structure improvement, circuit supplement, upgraded design method. Before development of the PLL, we simulated spectrum power, phase noise, harmonic characteristic by using ADS(Advanced Designed System). And, we compared result between measurement and simulation. Finally, we confirm a satisfying result which meet performance requirements between required standard and measured value. It will be useful for transceiver of service which operate in Ultra wideband.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1872-1879
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• 1994

The design and implementation of Ku-Band frequency synthesizer was accomplished by the use of PLL and frquency multiple method. Design procedure and operation characteristics of PLL circuit were analyzed on the basis of control theory to synthesize about 1 GHz frequency which should be stable. By connecting frequency doubler and frequency eighth multiplier to the designed PLL circuit in series, Ku-Band frequency was synthesized. The validity of design method of Ku-Band frequency synthesizer was verified through experimental results.

• Journal of the Microelectronics and Packaging Society
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• v.1 no.2
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• pp.143-146
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• 1994

본 연구에서는 900MHz PLL Module을 설계제조하였다. 제안된 PLL Module은 900MHz VCO 및 PLL Controller로 구성되었다. PLL Module의 출력레벨은 -2dBm이었다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.193-198
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• 2010

In this paper, we have introduced a new way to have low phase noise PLL of the Ultra wideband to meet performance requirements. Before development of the PLL, we simulated spectrum power, phase noise by using ADS. Finally, we confirm a satisfying result between required standard and measured value.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.368-371
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• 2000

The PLL(Phase-Locked Loop) techniques re employed to make the switching frequency of a resonant inverter follow the resonant frequency which may vary due to the load variations during operation. The conventional design guide of PLL is not suitable in these case since the inverter characteristics are not considered. In this paper the phase characteristics of a resonant inverter is analysed and added to the closed loop. And the design of PLL with digital phase detector is illustrated for the output frequency to track the resonant frequency of the inverter.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.3
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• pp.270-275
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• 2017

This paper proposes a double-phase-locked-loop (PLL) to improve the performance of position estimation in hall sensor-based permanent magnet synchronous motor control. In hall sensor-based control, a PLL is normally used to estimate the rotor position. The proposed Double-PLL consists of two PLLs, including a reset type integrator. The motor control is more accurate and has better performance than conventional PLL, such as a small estimated position ripple. The validity of the proposed algorithm is verified by simulations and experiments.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1231-1243
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• 2017

Grid-interactive power converters are normally synchronized with the grid using phase-locked loops (PLLs). The performance of the PLLs is affected by the non-ideal conditions in the sensed grid voltage such as harmonics, frequency deviations and the dc offsets in single-phase systems. In this paper, a single-phase PLL is presented to mitigate the effects of these non-idealities. This PLL is based on the popular second order generalized integrator (SOGI) structure. The SOGI structure is modified to eliminate the effects of input dc offsets. The resulting SOGI structure has a high-pass filtering property. Hence, this PLL is termed as a high-pass generalized integrator based PLL (HGI-PLL). It has fixed parameters which reduces the implementation complexity and aids in the implementation in low-end digital controllers. The HGI-PLL is shown to have the lowest resource utilization among the SOGI based PLLs with dc cancelling capability. Systematic design methods are evolved leading to a design that limits the unit vector THD to within 1% for given non-ideal input conditions in terms of frequency deviation and harmonic distortion. The proposed designs achieve the fastest transient response. The performance of this PLL has been verified experimentally. The results agree with the theoretical prediction.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.26-33
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• 1992

This paper describes a new phase-difference detection method and the associate process algorithm for calculating the mean value of phase difference detected and OVCXO control value and for monitoring and controlling the DP-PLL operation status to be used in the design of a high-frequency DP-PLL. Through the experiments of DP-PLL implemented with 16-bit processor, memories, pheriperals and OVCXO to eraluate the suggested method and algorithm, it is shown that a remarkable improvement in PLL function such as phase detection, and reference clock tracing capability, jitter absorbability and frequency stability compared with other existing DP-PLL synchronization device is achieved.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.15-20
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• 2002

In this project, we hale developed various techniques for subminiaturization, surface implementation, high frequency design, small-size SMD, performance test and application of the Dual PLL module, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation Dual PLL module design and fabrication techniques for an internationally competitive subminiature Dual PLL module.