• Journal of Advanced Marine Engineering and Technology
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• v.17 no.3
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• pp.60-69
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• 1993

The speed control associated with dc servo motors for direct-drive applications of mobile robot is considered in this study. Robot is moved by power wheeled steering of two dc servo motors mounted to it. In order to cooperate with micro-computer and to achieve the high-performance operation of dc servo motor, speed control system is composed of a digital Phase Locked Loop and H-type drive circuit. And the motor is driven by Pulse Width Modulations. In controlling PWM, it is modified to compose of H-type drive circuit with feedback diodes and switching transistor and design of control sequence so that it may show linear characteristics. As a result, speed characteristics of motor showed linear features. In order to get data on design of PLL control system, the parameters of 80[W[ motor & robot device is measured by simple software control. The PLL speed control system is schemed and designed by leaner drive circuit and measured parameters. A complete speed control system applied to 80[W] dc servo motor showed good linearity, stability and high response. Also, it is verified that the PLL speed control system has good compatibility as a mobile robot driver.

• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.3
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• pp.139-146
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• 1998

In this paper, we proposed the hybrid intelligent control method for fast response time and precise speed control of the AC Servo system. The proposed system first used the fuzzy-neural network control methods for fast response time and when the error reaches the preset value, used the PLL control method. In order to verify the advantage of he proposed method, the system is implemented. The results of the simulation and the experiment of speed control to use the 3-phase induction motor as a plant, we verified excellency of the proposed control method to compare with the conventional fuzzy-neural network control method.

• Proceedings of the KIPE Conference
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• 2014.11a
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• pp.87-88
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• 2014

The paper presents a novel phase locked loop(PLL) control method for robust three-phase thyristor dual converters under sag, notch, and phase loss conditions. This method is applied to three line to line voltages of grid to derive three phase angle errors from three separated single-phase PLLs. They can substitute for abnormal phase to guarantee the synchronization in the various grid fault conditions. The performance of novel PLL with moving average method is verified through simulations.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.132-135
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• 2008

This paper presents a PLL(Phase Lock Loop) control method for speed control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The Proposed PLL based speed control method uses a only phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.9
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• pp.562-568
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• 2004

The frequency and phase angle of the utility voltage are important in many industrial systems. In the three-phase system, they can be easily known by using the utility voltage vector. However, in the case of single phase system, there are some difficulties in detecting the information of utility voltage. In conventional system, the zero-crossing detection method is widely used, but could not obtain the information of utility voltage instantaneously. In this paper, the new digital PLL control using virtual two phase detector is proposed with a detailed analysis of single-phase digital PLL control for utility connected systems. The experimental results under various utility conditions are presented and demonstrate an excellent phase tracking capability in the single-phase grid-connected operation.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.1
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• pp.33-38
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• 2003

This paper describes control principles of the piezoelectric ultrasonic motor which is operated by the ultrasonic vibration generated by the piezoelectric element. The piezoelectric ultrasonic motor has excellent characteristics such as compact size, noiseless motion, low speed, high torque and controllability, and has been recently applied for the practical utilization in industrial, consumer, medical and automotive fields. In this paper, the design of two-phase push-pull inverter for driving the piezoelectric ultrasonic motor is described, and a new control method of automatic resonant frequency tracking using PLL(Phase-Locked Loop) technique is mainly presented. the experimental results by this inverter system for driving the piezoelectric ultrasonic motor are illustrated herein. The inverter system with PLL technique improved the speed stability of the piezoelectric ultrasonic motor.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.461-466
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• 1999

The switched reluctance motor (SRM) would have torque ripple if not operated with an MMF waveform specified for switching angle and phase voltage. This paper describes the robustic control scheme that permits the phase torque to be flat by PLL(Phase Locked Loop) controller. In this control scheme, the locked phase signal of PLL controls the switching dwell angle and it's loop filter signal controls the switching voltage adaptively. Experimental results show that stable dynamic performance is obtained for torque and speed together with low torque ripple on the operation of variable loads.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.778-782
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• 2004

본 논문에서는 전력 품질 기기의 제어에 있어서 필수적 요소라고 할 수 있는 전원각을 찾는 방법중에서 PLL(Phase Locked Loop)에 관하여 기존의 방식들을 먼저 알아보고, 정상분을 추출하여 이용하는 기존의 PLL 방식을 무정전전원장치에 적합한 형태로 개선한 주파수를 제한한 PLL 방식을 제안하였다. 제안된 PLL 방식은 기존의 PI 제어기에 주파수 제한기(limiter)와 안티 와인드업(anti-windup)을 추가하였다. 이것의 기본적인 동작 원리는 기존의 방법들과 같지만, 차이점은 주파수 제한기의 삽입으로 인하여 주파수 변동률을 일정한 범위 내에서 제한할 수 있다는 것이다. 기존의 PLL 방법과 본 논문에서 제안된 주파수를 제한한 PLL 방법의 차이를 알아보기 위하여 동적 전압 보상기로 전압을 보상하는 시뮬레이션을 하였고, 결과적으로 제안된 주파수를 제한한 PLL 방법이 기존의 PLL 방법보다 UPS에 적합함을 입증하였다.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.