• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.83-90
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• 2007

In this paper, we propose an implementation and an algorithm of 'Jitter and Glitch Removing Circuit' for UHF RFID reader system based on ISO/IEC 18000-6C standard. We analyze the response of TI(Texas Instrument) Gen2 tag with a reader using the proposed algorithm. In ISO/IEC 18000-6C standard, a bit rate accuracy(tolerance) is up to +/-22% during tag-to-interrogator communication and +/-1% during interrogator-to-tag communication. In order to solve tolerance problems, we implement the Jitter and Glitch Removing Circuit using the concept of tolerance and tolerance-accumulation instead of PLL(DPLL, ADPLL). The main clock is 19.2MHz and the LF(Link Frequency) is determined as 40kHz to meet the local radio regulation in korea. As a result of simulations, the error-rate is zero within 15% tolerance of tag responses. And in the case of using the adaptive LF generation circuit, the error-rate varies from 0.000589 to zero between 15% and 22% tolerance of tag responses. In conclusion, the error-rate is zero between 0%-22% tolerance of tag response specified in ISO/IEC 18000-6C standard.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.6
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• pp.100-108
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• 2005

In this paper deals with the frequency control of the HVDC scheme linking Haenam to Cheju Island. The primary aim of the study is to develop and evaluate a new frequency control that can be employed without having to utilise the existing Synchronous Compensators(Gas Turbines). Transient condition studies are performed utilising the detailed control strategies for the HVDC link, implemented in PSCAD/EMTDC. Study cases are completed involving synchronous compensators trip and load ripping events and study plots presented. It is demonstrated that the existing frequency measurement can be replaced by one derived from the AC network alone, incorporated into a new frequency control algorithm and gives effective frequency control and dynamic performance.

• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.394-396
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• 2006

When developing a new GPS receiver module, the essential problems are evaluation of reliable algorithms, software debugging, and performance comparison between algorithms to find optimal solution. Most GPS receiver modules nowadays use a correlator to track signals from satellites and an MCU (Micro Controller Unit) to control operations of the entire module. The problem of software evaluation from MCU is very difficult, due to limitation of MCU resources and low ability of interfacing with user. Normally, user has to expense special tool kit for a limiting access to MCU but it is also hard to use. This article introduces an implementation of a GPS receiver test bed using correlator GP2021 interfacing with ISA (Industry Standard Architecture) PC bus. This way can give user complete control and visibility into the operation of the receiver, then user can easily debug program and test algorithms. For this article, the least square method is implemented to test the hardware and software performance.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.12
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• pp.609-615
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• 2005

A 30kW electrical power conversion system is developed for a variable speed wind turbine. In the wind energy conversion system(WECS) a synchronous generator with field current excitation converts the mechanical energy into electrical energy. As the voltage and the frequency of the generator output vary according to the wind speed, a 6-bridge diode rectifier and a PWM boost chopper is utilized as an ac-dc converter maintaining the constant dc-link voltage with only single switch control. An input current control algorithm for maximum power generation during the variable speed operation is proposed without any usage of speed sensor. Grid connection type PWM inverter converts dc input power to ac output currents into the grid. The active power to the grid is controlled by q-axis current and the reactive power is controlled by d-axis current with appropriate decoupling. The phase angle of utility voltage is detected using software PLL(Phased Locked Loop) in d-q synchronous reference frame. Experimental results from the test of 30kW prototype wind turbine system show that the generator power can be controlled effectively during the variable speed operation without any speed sensor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.623-628
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• 2013

The retrodirective array antenna system is operated faster than existing techniques of beamforming due to its less complexity. Therefore, it is effective for beam tracking in the environment of fast vehicle. On the other hand, it also has difficulty in estimating AOA according to multipath environment or multiuser signals. To improve the certainty of estimating AOA), this article proposes hybrid digital retrodirective array antenna systme combined with MUSIC algorithm. In this paper, the digital retrodirective array antenna system is designed according to the number of antenna array by using only one digital PLL which finds angle of delayed phase. And we evaluate the performance of the digital retrodirective array antenna for the high speed tracking application. Performance is studied by simulink when the speed of mobile is 300km/h and the distance between transmitter and receiver is 100m and then we have to confirm the performance of the system in multi path environment. As a result, the mean of AOA (Angle Of Arrival) error is $4.2^{\circ}$ when SNR is 10dB and it is $1.3^{\circ}$ when SNR is 20dB. Consequently, the digital RDA shows very good performance for high speed tracking due to the simple calculation and realization.

• Journal of Power Electronics
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• v.18 no.1
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• pp.234-250
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• 2018

This paper presents a new load sharing control for use between paralleled three-phase inverters in an islanded microgrid based on the online line impedance estimation by the use of a Kalman filter. In this study, the mismatch of power sharing when the line impedance changes due to temperature, frequency, significant differences in line parameters and the requirements of the Plug-and-Play mode for inverters connected to a microgrid has been solved. In addition, this paper also presents a new droop control method working with the line impedance that is different from the traditional droop algorithm when the line impedance is assumed to be pure resistance or pure inductance. In this paper, the line impedance estimation for parallel inverters uses the minimum square method combined with a Kalman filter. In addition, the secondary control loops are designed to restore the voltage amplitude and frequency of a microgrid by using a combined nominal value SOGI-PLL with a generalized integral block and phase lock loop to monitor the exact voltage magnitude and frequency phase at the PCC. A control model has been simulated in Matlab/Simulink with three voltage source inverters connected in parallel for different ratios of power sharing. The simulation results demonstrate the accuracy of the proposed control method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.117-122
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• 2018

A large-capacity three-phase system air conditioner recently includes an inverter circuit to reduce power consumption. The inverter circuit uses a DC voltage that comes from DC-link power capacitor with the function of rectifying, which means AC voltage to DC voltage using a diode. An electrolytic capacitor is generally used to satisfy the voltage ripple and current ripple conditions of a DC-link power capacitor used for rectifying. Reducing the capacitance of the capacitor decreases the size, weight, and cost of the circuit. This paper proposes an algorithm to reduce the input ripple current by combining the minimum point estimation phase locked loop (PLL) phase control and the average voltage d axis current control technique. When this algorithm was used, the input ripple current decreased by almost 90%. The current ripple of the DC-link capacitor decreased due to the decrease in input ripple current. The capacitor capacity can be reduced but the electrolytic capacitor has a heat generation problem and life-time limitations because of its large equivalent series resistance (ESR). This paper proposes a method to select a film capacitor considering the current ripple at DC-link stage instead of an electrolytic capacitor. The capacitance was selected considering the voltage limitation, RMS (Root Mean Square) current capacity, and RMS current frequency analysis. A $1680{\mu}F$ electrolytic capacitor can be reduced to a $20{\mu}F$ film capacitor, which has the benefit of size, weight and cost. These results were verified by motor operation.