• Journal of the Korean Society for Precision Engineering
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• v.13 no.4
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• pp.24-33
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• 1996

PLCs are vital components of modern automation systems, which have penetrated into almost every industry. Many industries have a demand for facilitation of PLC programming. In this study, a programning system for sequential control is developed on a personal computer. This programming system consists of two main parts, a GRAFCET editor and a GRAFCET compiler. The GRAFCET editor enables us to model an actual sequential process by a GRAFCET diagram. This GRAFCET editor is developed by the menu-driven method based on specific menus and graphic symbols. The GRAFCET compiler consists of two parts, a GRAFCET parser and a code generator. The possible errors in a drawn GRAFCET diagram are first checked by the GRAFCET parser which generates finally an intermediate code from a verified CRAFCET diagram. Then the intermediate code is converted into a control code of an actual sequential controller by the code generator. To show the usefulness of this programming system, this system is applied to a pneumatically controlled handling robot. For this robot, a Z-80 microprocessor is used as the actual sequential controller.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.201-206
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• 2010

PLCs are special purpose microcontrollers used in most automatic control systems such as plants, embedded systems, and intelligent buildings. LD is one of the most popular languages among PLC languages. For now LD programs are mainly verified by simulation and testing which has a lot of limitation. This paper describes how to translate a given LD program into an input of a model checker so that LD program is verified by model checking. We define formal semantics of LD programs and SMV models and specify a formal definition of the translation function which preserves semantics between LD programs and SMV models.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2646-2648
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• 2001

In this paper, the development of Power Line Communication(PLC) device for white goods is presented. The commercial PLC chip-set is used for the modem device of white goods. As a PLC device for white goods, an ARM720 u-controller and a windows CE 3.0 are adopted. UPnP (Universal Plug and Play) that is applied for home network middle ware in implemented system. In addition, application programming and emulator for home appliance are implemented using UPnP standard ver 1.0.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.265-269
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• 2009

Formal specification plays important roles in guaranteeing software safety of safety-critical systems such as nuclear power plant's digital control systems. We had developed a technique [1] which synthesizes Function Block Diagram(FBD) programs from NuSCR formal requirements specifications, but it did not be used widely as it had no automatic tool support. FBD is one of the programming languages for Programmable Logic Controllers(PLC) based system. This paper introduces a CASE tool, NuSCRtoFBD, developed to automate the synthesis procedure. The CASE tool NuSCRtoFBD can reduce a number of errors occurred in the process of manual FBD programming.

• Journal of KIISE:Software and Applications
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• v.35 no.3
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• pp.149-161
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• 2008

As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.

• Journal of Korea Multimedia Society
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• v.11 no.8
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• pp.1072-1081
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• 2008

We can categorize the network address allocation mechanism into two types. One is to assign a unique network address using the address allocation server and the other is to make a random address by itself and process the DAD(Duplicate Address Detection) procedure. In this paper we suggest a new address allocation mechanism based on the signal strength for the PLC-based home network. As the combined mechanism of two types this mechanism allocates a unique address for the new node from one of the existing nodes with the simple equation and with the priority based on the signal strength from the new node to the existing nodes. We can use this mechanism for the self-healing function when the packet from the source node may not be delivered to the destination node directly. We developed the simulator for our mechanism using the C# programming and verified the network address assigned uniquely based on the signal strength.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10c
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• pp.526-529
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• 2007

산업자동화, 임베디드시스템, 지능형 빌딩, 유비쿼터스 환경 구축 등의 다양한 분야에 활용되는 PLC나 모션제어기를 위한 표준안은 IEC 61131-3이다. 이 표준안은 제어기를 위한 프로그래밍 환경과 언어의 문법구조를 정의하고 있으나, 도식적으로 표현되는 LD 프로그램의 저장 형식이 제시되지 않아서 관련 소프트웨어마다 서로 다른 저장 형식을 사용한다. PLCopen 그룹에서 배포한 표준 저장 형식 XML 스키마를 사용하면 데이터의 교환과 연동 언어들의 호환이 가능하다. 본 논문은 표준 XML 스키마를 기반하는 LD 그래픽편집기를 구현한다. 구현 형태는 Eclipse 플러그인으로서, Eclipse 도구인 EMF와 GEF를 이용하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.184-186
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• 2012

Function Block Diagram (FBD)는 산업용 컴퓨터인 Programmable Logic Controller (PLC)의 표준 프로그래밍 언어 중 하나이다. 다양한 시험 기법들의 오류 검출 효과성을 평가하기 위해 뮤테이션 분석 기법이 널리 쓰이고 있는데, FBD 모델 대상 뮤테이션 분석 기법에 대한 연구는 이루어지지 못하였다. 본 연구에서는 FBD 모델 대상 뮤테이션 분석 기법의 토대가 되는 FBD 모델 뮤테이션 연산자를 제안한다. 이를 위해서 FBD 모델의 특성, 다양한 FBD 모델링 오류, 기존의 뮤테이션 분석 기법에 관한 연구를 포괄적으로 분석하여 FBD 모델에 적합한 뮤테이션 연산자를 정의한다. 실제 산업계에서 쓰이는 FBD 모델을 대상으로 뮤테이션 연산자를 적용하고 평가한다.